Lines Matching refs:SRI
40 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
41 SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
42 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
43 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
44 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
45 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
46 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
47 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
48 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
49 SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
50 SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
51 SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
52 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
53 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
54 SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\
55 SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\
56 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
57 SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
58 SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
59 SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
60 SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
61 SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
62 SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
63 SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
64 SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
65 SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
66 SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
67 SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
68 SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
69 SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
70 SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
71 SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
72 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
73 SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
74 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
75 SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
76 SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
77 SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
78 SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
79 SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
80 SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
81 SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
82 SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
83 SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
84 SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
85 SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
86 SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
87 SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
88 SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
89 SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
90 SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
91 SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
92 SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
93 SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
94 SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
95 SRI(SMU_WM_CONTROL, WBIF, inst)