Lines Matching refs:hwseq

282 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_init_blank()
573 struct dce_hwseq *hws = dc->hwseq; in dcn20_plane_atomic_disable()
652 struct dce_hwseq *hws = dc->hwseq; in dcn20_enable_stream_timing()
717 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) in dcn20_enable_stream_timing()
718 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); in dcn20_enable_stream_timing()
919 struct dce_hwseq *hws = dc->hwseq; in dcn20_set_input_transfer_func()
1118 dcn20_power_on_plane(dc->hwseq, pipe_ctx); in dcn20_enable_plane()
1450 struct dce_hwseq *hws = dc->hwseq; in dcn20_update_dchubp_dpp()
1650 struct dce_hwseq *hws = dc->hwseq; in dcn20_program_pipe()
1737 struct dce_hwseq *hws = dc->hwseq; in dcn20_program_front_end_for_ctx()
1848 struct dce_hwseq *hwseq = dc->hwseq; in dcn20_post_unlock_program_front_end() local
1919 if (hwseq->funcs.program_mall_pipe_config) in dcn20_post_unlock_program_front_end()
1920 hwseq->funcs.program_mall_pipe_config(dc, context); in dcn20_post_unlock_program_front_end()
1923 if (hwseq->wa.DEGVIDCN21) in dcn20_post_unlock_program_front_end()
1928 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { in dcn20_post_unlock_program_front_end()
1937 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; in dcn20_post_unlock_program_front_end()
1938hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->… in dcn20_post_unlock_program_front_end()
2042 struct dce_hwseq *hws = dc->hwseq; in dcn20_update_bandwidth()
2162 struct dce_hwseq *hws = dc->hwseq; in dcn20_disable_stream_gating()
2177 struct dce_hwseq *hws = dc->hwseq; in dcn20_enable_stream_gating()
2312 struct dce_hwseq *hws = link->dc->hwseq; in dcn20_unblank_stream()
2447 struct dce_hwseq *hws = dc->hwseq; in dcn20_reset_hw_ctx_wrap()
2595 if (dc->hwseq->funcs.setup_hpo_hw_control) in dcn20_enable_stream()
2596 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); in dcn20_enable_stream()
2625 if (dc->hwseq->funcs.set_pixels_per_cycle) in dcn20_enable_stream()
2626 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); in dcn20_enable_stream()
2666 struct dce_hwseq *hws = dc->hwseq; in dcn20_fpga_init_hw()