Lines Matching refs:SRI
40 #define SRI(reg_name, block, id)\ macro
54 SRI(WB_ENABLE, CNV, inst),\
55 SRI(WB_EC_CONFIG, CNV, inst),\
56 SRI(CNV_MODE, CNV, inst),\
57 SRI(WB_SOFT_RESET, CNV, inst),\
58 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
59 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
60 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
61 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
62 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
63 SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
64 SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
65 SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
66 SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
67 SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
68 SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
69 SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
70 SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
71 SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
72 SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
73 SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
74 SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
75 SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
76 SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
77 SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
78 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
79 SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
80 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
81 SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
82 SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
83 SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
84 SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)