Lines Matching refs:pool
800 static void dce80_resource_destruct(struct dce110_resource_pool *pool) in dce80_resource_destruct() argument
804 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
805 if (pool->base.opps[i] != NULL) in dce80_resource_destruct()
806 dce110_opp_destroy(&pool->base.opps[i]); in dce80_resource_destruct()
808 if (pool->base.transforms[i] != NULL) in dce80_resource_destruct()
809 dce80_transform_destroy(&pool->base.transforms[i]); in dce80_resource_destruct()
811 if (pool->base.ipps[i] != NULL) in dce80_resource_destruct()
812 dce_ipp_destroy(&pool->base.ipps[i]); in dce80_resource_destruct()
814 if (pool->base.mis[i] != NULL) { in dce80_resource_destruct()
815 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce80_resource_destruct()
816 pool->base.mis[i] = NULL; in dce80_resource_destruct()
819 if (pool->base.timing_generators[i] != NULL) { in dce80_resource_destruct()
820 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); in dce80_resource_destruct()
821 pool->base.timing_generators[i] = NULL; in dce80_resource_destruct()
825 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
826 if (pool->base.engines[i] != NULL) in dce80_resource_destruct()
827 dce110_engine_destroy(&pool->base.engines[i]); in dce80_resource_destruct()
828 if (pool->base.hw_i2cs[i] != NULL) { in dce80_resource_destruct()
829 kfree(pool->base.hw_i2cs[i]); in dce80_resource_destruct()
830 pool->base.hw_i2cs[i] = NULL; in dce80_resource_destruct()
832 if (pool->base.sw_i2cs[i] != NULL) { in dce80_resource_destruct()
833 kfree(pool->base.sw_i2cs[i]); in dce80_resource_destruct()
834 pool->base.sw_i2cs[i] = NULL; in dce80_resource_destruct()
838 for (i = 0; i < pool->base.stream_enc_count; i++) { in dce80_resource_destruct()
839 if (pool->base.stream_enc[i] != NULL) in dce80_resource_destruct()
840 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); in dce80_resource_destruct()
843 for (i = 0; i < pool->base.clk_src_count; i++) { in dce80_resource_destruct()
844 if (pool->base.clock_sources[i] != NULL) { in dce80_resource_destruct()
845 dce80_clock_source_destroy(&pool->base.clock_sources[i]); in dce80_resource_destruct()
849 if (pool->base.abm != NULL) in dce80_resource_destruct()
850 dce_abm_destroy(&pool->base.abm); in dce80_resource_destruct()
852 if (pool->base.dmcu != NULL) in dce80_resource_destruct()
853 dce_dmcu_destroy(&pool->base.dmcu); in dce80_resource_destruct()
855 if (pool->base.dp_clock_source != NULL) in dce80_resource_destruct()
856 dce80_clock_source_destroy(&pool->base.dp_clock_source); in dce80_resource_destruct()
858 for (i = 0; i < pool->base.audio_count; i++) { in dce80_resource_destruct()
859 if (pool->base.audios[i] != NULL) { in dce80_resource_destruct()
860 dce_aud_destroy(&pool->base.audios[i]); in dce80_resource_destruct()
864 if (pool->base.irqs != NULL) { in dce80_resource_destruct()
865 dal_irq_service_destroy(&pool->base.irqs); in dce80_resource_destruct()
924 static void dce80_destroy_resource_pool(struct resource_pool **pool) in dce80_destroy_resource_pool() argument
926 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); in dce80_destroy_resource_pool()
930 *pool = NULL; in dce80_destroy_resource_pool()
947 struct dce110_resource_pool *pool) in dce80_construct() argument
955 pool->base.res_cap = &res_cap; in dce80_construct()
956 pool->base.funcs = &dce80_res_pool_funcs; in dce80_construct()
962 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce80_construct()
963 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
964 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
980 pool->base.dp_clock_source = in dce80_construct()
983 pool->base.clock_sources[0] = in dce80_construct()
985 pool->base.clock_sources[1] = in dce80_construct()
987 pool->base.clock_sources[2] = in dce80_construct()
989 pool->base.clk_src_count = 3; in dce80_construct()
992 pool->base.dp_clock_source = in dce80_construct()
995 pool->base.clock_sources[0] = in dce80_construct()
997 pool->base.clock_sources[1] = in dce80_construct()
999 pool->base.clk_src_count = 2; in dce80_construct()
1002 if (pool->base.dp_clock_source == NULL) { in dce80_construct()
1008 for (i = 0; i < pool->base.clk_src_count; i++) { in dce80_construct()
1009 if (pool->base.clock_sources[i] == NULL) { in dce80_construct()
1016 pool->base.dmcu = dce_dmcu_create(ctx, in dce80_construct()
1020 if (pool->base.dmcu == NULL) { in dce80_construct()
1026 pool->base.abm = dce_abm_create(ctx, in dce80_construct()
1030 if (pool->base.abm == NULL) { in dce80_construct()
1039 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce80_construct()
1040 if (!pool->base.irqs) in dce80_construct()
1044 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1045 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce80_construct()
1047 if (pool->base.timing_generators[i] == NULL) { in dce80_construct()
1053 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce80_construct()
1054 if (pool->base.mis[i] == NULL) { in dce80_construct()
1060 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce80_construct()
1061 if (pool->base.ipps[i] == NULL) { in dce80_construct()
1067 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce80_construct()
1068 if (pool->base.transforms[i] == NULL) { in dce80_construct()
1074 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce80_construct()
1075 if (pool->base.opps[i] == NULL) { in dce80_construct()
1082 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1083 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce80_construct()
1084 if (pool->base.engines[i] == NULL) { in dce80_construct()
1090 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce80_construct()
1091 if (pool->base.hw_i2cs[i] == NULL) { in dce80_construct()
1097 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce80_construct()
1098 if (pool->base.sw_i2cs[i] == NULL) { in dce80_construct()
1106 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1113 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce80_construct()
1123 dce80_resource_destruct(pool); in dce80_construct()
1131 struct dce110_resource_pool *pool = in dce80_create_resource_pool() local
1134 if (!pool) in dce80_create_resource_pool()
1137 if (dce80_construct(num_virtual_links, dc, pool)) in dce80_create_resource_pool()
1138 return &pool->base; in dce80_create_resource_pool()
1140 kfree(pool); in dce80_create_resource_pool()
1148 struct dce110_resource_pool *pool) in dce81_construct() argument
1156 pool->base.res_cap = &res_cap_81; in dce81_construct()
1157 pool->base.funcs = &dce80_res_pool_funcs; in dce81_construct()
1163 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce81_construct()
1164 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1165 pool->base.timing_generator_count = res_cap_81.num_timing_generator; in dce81_construct()
1180 pool->base.dp_clock_source = in dce81_construct()
1183 pool->base.clock_sources[0] = in dce81_construct()
1185 pool->base.clock_sources[1] = in dce81_construct()
1187 pool->base.clock_sources[2] = in dce81_construct()
1189 pool->base.clk_src_count = 3; in dce81_construct()
1192 pool->base.dp_clock_source = in dce81_construct()
1195 pool->base.clock_sources[0] = in dce81_construct()
1197 pool->base.clock_sources[1] = in dce81_construct()
1199 pool->base.clk_src_count = 2; in dce81_construct()
1202 if (pool->base.dp_clock_source == NULL) { in dce81_construct()
1208 for (i = 0; i < pool->base.clk_src_count; i++) { in dce81_construct()
1209 if (pool->base.clock_sources[i] == NULL) { in dce81_construct()
1216 pool->base.dmcu = dce_dmcu_create(ctx, in dce81_construct()
1220 if (pool->base.dmcu == NULL) { in dce81_construct()
1226 pool->base.abm = dce_abm_create(ctx, in dce81_construct()
1230 if (pool->base.abm == NULL) { in dce81_construct()
1239 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce81_construct()
1240 if (!pool->base.irqs) in dce81_construct()
1244 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1245 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce81_construct()
1247 if (pool->base.timing_generators[i] == NULL) { in dce81_construct()
1253 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce81_construct()
1254 if (pool->base.mis[i] == NULL) { in dce81_construct()
1260 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce81_construct()
1261 if (pool->base.ipps[i] == NULL) { in dce81_construct()
1267 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce81_construct()
1268 if (pool->base.transforms[i] == NULL) { in dce81_construct()
1274 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce81_construct()
1275 if (pool->base.opps[i] == NULL) { in dce81_construct()
1282 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1283 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce81_construct()
1284 if (pool->base.engines[i] == NULL) { in dce81_construct()
1290 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce81_construct()
1291 if (pool->base.hw_i2cs[i] == NULL) { in dce81_construct()
1297 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce81_construct()
1298 if (pool->base.sw_i2cs[i] == NULL) { in dce81_construct()
1306 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1313 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce81_construct()
1323 dce80_resource_destruct(pool); in dce81_construct()
1331 struct dce110_resource_pool *pool = in dce81_create_resource_pool() local
1334 if (!pool) in dce81_create_resource_pool()
1337 if (dce81_construct(num_virtual_links, dc, pool)) in dce81_create_resource_pool()
1338 return &pool->base; in dce81_create_resource_pool()
1340 kfree(pool); in dce81_create_resource_pool()
1348 struct dce110_resource_pool *pool) in dce83_construct() argument
1356 pool->base.res_cap = &res_cap_83; in dce83_construct()
1357 pool->base.funcs = &dce80_res_pool_funcs; in dce83_construct()
1363 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce83_construct()
1364 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1365 pool->base.timing_generator_count = res_cap_83.num_timing_generator; in dce83_construct()
1380 pool->base.dp_clock_source = in dce83_construct()
1383 pool->base.clock_sources[0] = in dce83_construct()
1385 pool->base.clock_sources[1] = in dce83_construct()
1387 pool->base.clk_src_count = 2; in dce83_construct()
1390 pool->base.dp_clock_source = in dce83_construct()
1393 pool->base.clock_sources[0] = in dce83_construct()
1395 pool->base.clk_src_count = 1; in dce83_construct()
1398 if (pool->base.dp_clock_source == NULL) { in dce83_construct()
1404 for (i = 0; i < pool->base.clk_src_count; i++) { in dce83_construct()
1405 if (pool->base.clock_sources[i] == NULL) { in dce83_construct()
1412 pool->base.dmcu = dce_dmcu_create(ctx, in dce83_construct()
1416 if (pool->base.dmcu == NULL) { in dce83_construct()
1422 pool->base.abm = dce_abm_create(ctx, in dce83_construct()
1426 if (pool->base.abm == NULL) { in dce83_construct()
1435 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce83_construct()
1436 if (!pool->base.irqs) in dce83_construct()
1440 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
1441 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce83_construct()
1443 if (pool->base.timing_generators[i] == NULL) { in dce83_construct()
1449 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce83_construct()
1450 if (pool->base.mis[i] == NULL) { in dce83_construct()
1456 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce83_construct()
1457 if (pool->base.ipps[i] == NULL) { in dce83_construct()
1463 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce83_construct()
1464 if (pool->base.transforms[i] == NULL) { in dce83_construct()
1470 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce83_construct()
1471 if (pool->base.opps[i] == NULL) { in dce83_construct()
1478 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
1479 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce83_construct()
1480 if (pool->base.engines[i] == NULL) { in dce83_construct()
1486 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce83_construct()
1487 if (pool->base.hw_i2cs[i] == NULL) { in dce83_construct()
1493 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce83_construct()
1494 if (pool->base.sw_i2cs[i] == NULL) { in dce83_construct()
1502 dc->caps.max_planes = pool->base.pipe_count; in dce83_construct()
1509 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce83_construct()
1519 dce80_resource_destruct(pool); in dce83_construct()
1527 struct dce110_resource_pool *pool = in dce83_create_resource_pool() local
1530 if (!pool) in dce83_create_resource_pool()
1533 if (dce83_construct(num_virtual_links, dc, pool)) in dce83_create_resource_pool()
1534 return &pool->base; in dce83_create_resource_pool()