Lines Matching refs:SR
45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
106 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
107 SR(DCFEV_CLOCK_CONTROL), \
116 SR(BLNDV_CONTROL),\
157 SR(DCHUB_FB_LOCATION),\
158 SR(DCHUB_AGP_BASE),\
159 SR(DCHUB_AGP_BOT),\
160 SR(DCHUB_AGP_TOP)
172 SR(REFCLK_CNTL), \
173 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
174 SR(DIO_MEM_PWR_CTRL), \
175 SR(DCCG_GATE_DISABLE_CNTL), \
176 SR(DCCG_GATE_DISABLE_CNTL2), \
177 SR(DCFCLK_CNTL),\
178 SR(DCFCLK_CNTL), \
179 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
205 SR(DCHUBBUB_SDPIF_FB_BASE),\
206 SR(DCHUBBUB_SDPIF_FB_OFFSET),\
207 SR(DCHUBBUB_SDPIF_AGP_BASE),\
208 SR(DCHUBBUB_SDPIF_AGP_BOT),\
209 SR(DCHUBBUB_SDPIF_AGP_TOP),\
210 SR(DOMAIN0_PG_CONFIG), \
211 SR(DOMAIN1_PG_CONFIG), \
212 SR(DOMAIN2_PG_CONFIG), \
213 SR(DOMAIN3_PG_CONFIG), \
214 SR(DOMAIN4_PG_CONFIG), \
215 SR(DOMAIN5_PG_CONFIG), \
216 SR(DOMAIN6_PG_CONFIG), \
217 SR(DOMAIN7_PG_CONFIG), \
218 SR(DOMAIN0_PG_STATUS), \
219 SR(DOMAIN1_PG_STATUS), \
220 SR(DOMAIN2_PG_STATUS), \
221 SR(DOMAIN3_PG_STATUS), \
222 SR(DOMAIN4_PG_STATUS), \
223 SR(DOMAIN5_PG_STATUS), \
224 SR(DOMAIN6_PG_STATUS), \
225 SR(DOMAIN7_PG_STATUS), \
226 SR(D1VGA_CONTROL), \
227 SR(D2VGA_CONTROL), \
228 SR(D3VGA_CONTROL), \
229 SR(D4VGA_CONTROL), \
230 SR(VGA_TEST_CONTROL), \
231 SR(DC_IP_REQUEST_CNTL)
241 SR(MICROSECOND_TIME_BASE_DIV), \
242 SR(MILLISECOND_TIME_BASE_DIV), \
243 SR(DISPCLK_FREQ_CHANGE_CNTL), \
244 SR(RBBMIF_TIMEOUT_DIS), \
245 SR(RBBMIF_TIMEOUT_DIS_2), \
246 SR(DCHUBBUB_CRC_CTRL), \
247 SR(DPP_TOP0_DPP_CRC_CTRL), \
248 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
249 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
250 SR(MPC_CRC_CTRL), \
251 SR(MPC_CRC_RESULT_GB), \
252 SR(MPC_CRC_RESULT_C), \
253 SR(MPC_CRC_RESULT_AR), \
254 SR(DOMAIN0_PG_CONFIG), \
255 SR(DOMAIN1_PG_CONFIG), \
256 SR(DOMAIN2_PG_CONFIG), \
257 SR(DOMAIN3_PG_CONFIG), \
258 SR(DOMAIN4_PG_CONFIG), \
259 SR(DOMAIN5_PG_CONFIG), \
260 SR(DOMAIN6_PG_CONFIG), \
261 SR(DOMAIN7_PG_CONFIG), \
262 SR(DOMAIN8_PG_CONFIG), \
263 SR(DOMAIN9_PG_CONFIG), \
266 SR(DOMAIN16_PG_CONFIG), \
267 SR(DOMAIN17_PG_CONFIG), \
268 SR(DOMAIN18_PG_CONFIG), \
269 SR(DOMAIN19_PG_CONFIG), \
270 SR(DOMAIN20_PG_CONFIG), \
271 SR(DOMAIN21_PG_CONFIG), \
272 SR(DOMAIN0_PG_STATUS), \
273 SR(DOMAIN1_PG_STATUS), \
274 SR(DOMAIN2_PG_STATUS), \
275 SR(DOMAIN3_PG_STATUS), \
276 SR(DOMAIN4_PG_STATUS), \
277 SR(DOMAIN5_PG_STATUS), \
278 SR(DOMAIN6_PG_STATUS), \
279 SR(DOMAIN7_PG_STATUS), \
280 SR(DOMAIN8_PG_STATUS), \
281 SR(DOMAIN9_PG_STATUS), \
282 SR(DOMAIN10_PG_STATUS), \
283 SR(DOMAIN11_PG_STATUS), \
284 SR(DOMAIN16_PG_STATUS), \
285 SR(DOMAIN17_PG_STATUS), \
286 SR(DOMAIN18_PG_STATUS), \
287 SR(DOMAIN19_PG_STATUS), \
288 SR(DOMAIN20_PG_STATUS), \
289 SR(DOMAIN21_PG_STATUS), \
290 SR(D1VGA_CONTROL), \
291 SR(D2VGA_CONTROL), \
292 SR(D3VGA_CONTROL), \
293 SR(D4VGA_CONTROL), \
294 SR(D5VGA_CONTROL), \
295 SR(D6VGA_CONTROL), \
296 SR(DC_IP_REQUEST_CNTL)
305 SR(MICROSECOND_TIME_BASE_DIV), \
306 SR(MILLISECOND_TIME_BASE_DIV), \
307 SR(DISPCLK_FREQ_CHANGE_CNTL), \
308 SR(RBBMIF_TIMEOUT_DIS), \
309 SR(RBBMIF_TIMEOUT_DIS_2), \
310 SR(DCHUBBUB_CRC_CTRL), \
311 SR(DPP_TOP0_DPP_CRC_CTRL), \
312 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
313 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
314 SR(MPC_CRC_CTRL), \
315 SR(MPC_CRC_RESULT_GB), \
316 SR(MPC_CRC_RESULT_C), \
317 SR(MPC_CRC_RESULT_AR), \
318 SR(DOMAIN0_PG_CONFIG), \
319 SR(DOMAIN1_PG_CONFIG), \
320 SR(DOMAIN2_PG_CONFIG), \
321 SR(DOMAIN3_PG_CONFIG), \
322 SR(DOMAIN4_PG_CONFIG), \
323 SR(DOMAIN5_PG_CONFIG), \
324 SR(DOMAIN6_PG_CONFIG), \
325 SR(DOMAIN7_PG_CONFIG), \
326 SR(DOMAIN16_PG_CONFIG), \
327 SR(DOMAIN17_PG_CONFIG), \
328 SR(DOMAIN18_PG_CONFIG), \
329 SR(DOMAIN0_PG_STATUS), \
330 SR(DOMAIN1_PG_STATUS), \
331 SR(DOMAIN2_PG_STATUS), \
332 SR(DOMAIN3_PG_STATUS), \
333 SR(DOMAIN4_PG_STATUS), \
334 SR(DOMAIN5_PG_STATUS), \
335 SR(DOMAIN6_PG_STATUS), \
336 SR(DOMAIN7_PG_STATUS), \
337 SR(DOMAIN16_PG_STATUS), \
338 SR(DOMAIN17_PG_STATUS), \
339 SR(DOMAIN18_PG_STATUS), \
340 SR(D1VGA_CONTROL), \
341 SR(D2VGA_CONTROL), \
342 SR(D3VGA_CONTROL), \
343 SR(D4VGA_CONTROL), \
344 SR(D5VGA_CONTROL), \
345 SR(D6VGA_CONTROL), \
346 SR(DC_IP_REQUEST_CNTL)
352 SR(MICROSECOND_TIME_BASE_DIV), \
353 SR(MILLISECOND_TIME_BASE_DIV), \
354 SR(DISPCLK_FREQ_CHANGE_CNTL), \
355 SR(RBBMIF_TIMEOUT_DIS), \
356 SR(RBBMIF_TIMEOUT_DIS_2), \
357 SR(DCHUBBUB_CRC_CTRL), \
358 SR(DPP_TOP0_DPP_CRC_CTRL), \
359 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
360 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
361 SR(MPC_CRC_CTRL), \
362 SR(MPC_CRC_RESULT_GB), \
363 SR(MPC_CRC_RESULT_C), \
364 SR(MPC_CRC_RESULT_AR), \
365 SR(AZALIA_AUDIO_DTO), \
366 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
376 SR(MICROSECOND_TIME_BASE_DIV), \
377 SR(MILLISECOND_TIME_BASE_DIV), \
378 SR(DISPCLK_FREQ_CHANGE_CNTL), \
379 SR(RBBMIF_TIMEOUT_DIS), \
380 SR(RBBMIF_TIMEOUT_DIS_2), \
381 SR(DCHUBBUB_CRC_CTRL), \
382 SR(DPP_TOP0_DPP_CRC_CTRL), \
383 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
384 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
385 SR(MPC_CRC_CTRL), \
386 SR(MPC_CRC_RESULT_GB), \
387 SR(MPC_CRC_RESULT_C), \
388 SR(MPC_CRC_RESULT_AR), \
389 SR(AZALIA_AUDIO_DTO), \
390 SR(AZALIA_CONTROLLER_CLOCK_GATING)
393 SR(REFCLK_CNTL), \
394 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
395 SR(DIO_MEM_PWR_CTRL), \
396 SR(DCCG_GATE_DISABLE_CNTL), \
397 SR(DCCG_GATE_DISABLE_CNTL2), \
398 SR(DCFCLK_CNTL),\
399 SR(DCFCLK_CNTL), \
400 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
409 SR(MICROSECOND_TIME_BASE_DIV), \
410 SR(MILLISECOND_TIME_BASE_DIV), \
411 SR(DISPCLK_FREQ_CHANGE_CNTL), \
412 SR(RBBMIF_TIMEOUT_DIS), \
413 SR(RBBMIF_TIMEOUT_DIS_2), \
414 SR(DCHUBBUB_CRC_CTRL), \
415 SR(DPP_TOP0_DPP_CRC_CTRL), \
416 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
417 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
418 SR(MPC_CRC_CTRL), \
419 SR(MPC_CRC_RESULT_GB), \
420 SR(MPC_CRC_RESULT_C), \
421 SR(MPC_CRC_RESULT_AR), \
422 SR(DOMAIN0_PG_CONFIG), \
423 SR(DOMAIN1_PG_CONFIG), \
424 SR(DOMAIN2_PG_CONFIG), \
425 SR(DOMAIN3_PG_CONFIG), \
426 SR(DOMAIN4_PG_CONFIG), \
427 SR(DOMAIN5_PG_CONFIG), \
428 SR(DOMAIN6_PG_CONFIG), \
429 SR(DOMAIN7_PG_CONFIG), \
430 SR(DOMAIN16_PG_CONFIG), \
431 SR(DOMAIN17_PG_CONFIG), \
432 SR(DOMAIN18_PG_CONFIG), \
433 SR(DOMAIN0_PG_STATUS), \
434 SR(DOMAIN1_PG_STATUS), \
435 SR(DOMAIN2_PG_STATUS), \
436 SR(DOMAIN3_PG_STATUS), \
437 SR(DOMAIN4_PG_STATUS), \
438 SR(DOMAIN5_PG_STATUS), \
439 SR(DOMAIN6_PG_STATUS), \
440 SR(DOMAIN7_PG_STATUS), \
441 SR(DOMAIN16_PG_STATUS), \
442 SR(DOMAIN17_PG_STATUS), \
443 SR(DOMAIN18_PG_STATUS), \
444 SR(D1VGA_CONTROL), \
445 SR(D2VGA_CONTROL), \
446 SR(D3VGA_CONTROL), \
447 SR(D4VGA_CONTROL), \
448 SR(D5VGA_CONTROL), \
449 SR(D6VGA_CONTROL), \
450 SR(DC_IP_REQUEST_CNTL), \
451 SR(AZALIA_AUDIO_DTO), \
452 SR(AZALIA_CONTROLLER_CLOCK_GATING)
461 SR(MICROSECOND_TIME_BASE_DIV), \
462 SR(MILLISECOND_TIME_BASE_DIV), \
463 SR(DISPCLK_FREQ_CHANGE_CNTL), \
464 SR(RBBMIF_TIMEOUT_DIS), \
465 SR(RBBMIF_TIMEOUT_DIS_2), \
466 SR(DCHUBBUB_CRC_CTRL), \
467 SR(DPP_TOP0_DPP_CRC_CTRL), \
468 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
469 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
470 SR(MPC_CRC_CTRL), \
471 SR(MPC_CRC_RESULT_GB), \
472 SR(MPC_CRC_RESULT_C), \
473 SR(MPC_CRC_RESULT_AR), \
474 SR(DOMAIN0_PG_CONFIG), \
475 SR(DOMAIN1_PG_CONFIG), \
476 SR(DOMAIN2_PG_CONFIG), \
477 SR(DOMAIN3_PG_CONFIG), \
478 SR(DOMAIN4_PG_CONFIG), \
479 SR(DOMAIN5_PG_CONFIG), \
480 SR(DOMAIN6_PG_CONFIG), \
481 SR(DOMAIN7_PG_CONFIG), \
482 SR(DOMAIN8_PG_CONFIG), \
483 SR(DOMAIN9_PG_CONFIG), \
484 SR(DOMAIN16_PG_CONFIG), \
485 SR(DOMAIN17_PG_CONFIG), \
486 SR(DOMAIN18_PG_CONFIG), \
487 SR(DOMAIN19_PG_CONFIG), \
488 SR(DOMAIN20_PG_CONFIG), \
489 SR(DOMAIN0_PG_STATUS), \
490 SR(DOMAIN1_PG_STATUS), \
491 SR(DOMAIN2_PG_STATUS), \
492 SR(DOMAIN3_PG_STATUS), \
493 SR(DOMAIN4_PG_STATUS), \
494 SR(DOMAIN5_PG_STATUS), \
495 SR(DOMAIN6_PG_STATUS), \
496 SR(DOMAIN7_PG_STATUS), \
497 SR(DOMAIN8_PG_STATUS), \
498 SR(DOMAIN9_PG_STATUS), \
499 SR(DOMAIN16_PG_STATUS), \
500 SR(DOMAIN17_PG_STATUS), \
501 SR(DOMAIN18_PG_STATUS), \
502 SR(DOMAIN19_PG_STATUS), \
503 SR(DOMAIN20_PG_STATUS), \
504 SR(D1VGA_CONTROL), \
505 SR(D2VGA_CONTROL), \
506 SR(D3VGA_CONTROL), \
507 SR(D4VGA_CONTROL), \
508 SR(D5VGA_CONTROL), \
509 SR(D6VGA_CONTROL), \
510 SR(DC_IP_REQUEST_CNTL), \
511 SR(AZALIA_AUDIO_DTO), \
512 SR(AZALIA_CONTROLLER_CLOCK_GATING)
518 SR(MICROSECOND_TIME_BASE_DIV), \
519 SR(MILLISECOND_TIME_BASE_DIV), \
520 SR(DISPCLK_FREQ_CHANGE_CNTL), \
521 SR(RBBMIF_TIMEOUT_DIS), \
522 SR(RBBMIF_TIMEOUT_DIS_2), \
523 SR(DCHUBBUB_CRC_CTRL), \
524 SR(DPP_TOP0_DPP_CRC_CTRL), \
525 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
526 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
527 SR(MPC_CRC_CTRL), \
528 SR(MPC_CRC_RESULT_GB), \
529 SR(MPC_CRC_RESULT_C), \
530 SR(MPC_CRC_RESULT_AR), \
531 SR(D1VGA_CONTROL), \
532 SR(D2VGA_CONTROL), \
533 SR(D3VGA_CONTROL), \
534 SR(D4VGA_CONTROL), \
535 SR(D5VGA_CONTROL), \
536 SR(D6VGA_CONTROL), \
539 SR(AZALIA_AUDIO_DTO), \
540 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
541 SR(HPO_TOP_CLOCK_CONTROL)