115 		volatile struct amdgpu_vcn4_fw_shared *fw_shared;  in vcn_v4_0_sw_init()  local
142 		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;  in vcn_v4_0_sw_init()
143 		fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);  in vcn_v4_0_sw_init()
144 		fw_shared->sq.is_enabled = 1;  in vcn_v4_0_sw_init()
146 		fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);  in vcn_v4_0_sw_init()
147 		fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?  in vcn_v4_0_sw_init()
151 			fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);  in vcn_v4_0_sw_init()
183 			volatile struct amdgpu_vcn4_fw_shared *fw_shared;  in vcn_v4_0_sw_fini()  local
188 			fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;  in vcn_v4_0_sw_fini()
189 			fw_shared->present_flag_0 = 0;  in vcn_v4_0_sw_fini()
190 			fw_shared->sq.is_enabled = 0;  in vcn_v4_0_sw_fini()
391 		lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));  in vcn_v4_0_mc_resume()
393 		upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));  in vcn_v4_0_mc_resume()
491 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
494 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
866 	volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;  in vcn_v4_0_start_dpg_mode()  local
963 	fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;  in vcn_v4_0_start_dpg_mode()
974 	fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);  in vcn_v4_0_start_dpg_mode()
993 	volatile struct amdgpu_vcn4_fw_shared *fw_shared;  in vcn_v4_0_start()  local
1002 		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;  in vcn_v4_0_start()
1146 		fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;  in vcn_v4_0_start()
1157 		fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);  in vcn_v4_0_start()
1188 	volatile struct amdgpu_vcn4_fw_shared *fw_shared;  in vcn_v4_0_start_sriov()  local
1277 		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;  in vcn_v4_0_start_sriov()
1278 		rb_setup = &fw_shared->rb_setup;  in vcn_v4_0_start_sriov()
1288 		fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);  in vcn_v4_0_start_sriov()
1292 			lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));  in vcn_v4_0_start_sriov()
1295 			upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));  in vcn_v4_0_start_sriov()
1408 	volatile struct amdgpu_vcn4_fw_shared *fw_shared;  in vcn_v4_0_stop()  local
1413 		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;  in vcn_v4_0_stop()
1414 		fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;  in vcn_v4_0_stop()