Lines Matching refs:WREG32_SOC15
357 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
359 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
361 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v4_0_mc_resume()
364 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
366 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
369 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_mc_resume()
371 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v4_0_mc_resume()
374 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
376 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
378 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_mc_resume()
379 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_mc_resume()
382 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
384 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
386 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v4_0_mc_resume()
387 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_mc_resume()
390 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
392 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
394 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v4_0_mc_resume()
395 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, in vcn_v4_0_mc_resume()
534 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); in vcn_v4_0_disable_static_power_gating()
556 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); in vcn_v4_0_disable_static_power_gating()
566 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); in vcn_v4_0_disable_static_power_gating()
588 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); in vcn_v4_0_enable_static_power_gating()
604 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); in vcn_v4_0_enable_static_power_gating()
646 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
670 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); in vcn_v4_0_disable_clock_gating()
694 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
721 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); in vcn_v4_0_disable_clock_gating()
734 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
814 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
837 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
850 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
877 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); in vcn_v4_0_start_dpg_mode()
956 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v4_0_start_dpg_mode()
957 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v4_0_start_dpg_mode()
958 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v4_0_start_dpg_mode()
962 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
964 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); in vcn_v4_0_start_dpg_mode()
965 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); in vcn_v4_0_start_dpg_mode()
968 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); in vcn_v4_0_start_dpg_mode()
973 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
976 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, in vcn_v4_0_start_dpg_mode()
1014 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); in vcn_v4_0_start()
1034 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_start()
1038 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | in vcn_v4_0_start()
1048 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); in vcn_v4_0_start()
1051 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, in vcn_v4_0_start()
1058 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, in vcn_v4_0_start()
1065 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, in vcn_v4_0_start()
1073 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, in vcn_v4_0_start()
1135 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, in vcn_v4_0_start()
1139 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v4_0_start()
1140 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v4_0_start()
1141 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v4_0_start()
1145 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
1147 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); in vcn_v4_0_start()
1148 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); in vcn_v4_0_start()
1151 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); in vcn_v4_0_start()
1156 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
1320 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); in vcn_v4_0_start_sriov()
1321 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); in vcn_v4_0_start_sriov()
1328 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); in vcn_v4_0_start_sriov()
1332 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); in vcn_v4_0_start_sriov()
1335 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); in vcn_v4_0_start_sriov()
1341 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); in vcn_v4_0_start_sriov()
1437 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); in vcn_v4_0_stop()
1461 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_stop()
1464 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_stop()
1467 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); in vcn_v4_0_stop()
1511 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v4_0_pause_dpg_mode()
1524 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v4_0_pause_dpg_mode()
1587 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v4_0_unified_ring_set_wptr()