Lines Matching refs:WREG32_SOC15
338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
340 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
342 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
345 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
347 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
350 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_0_mc_resume()
354 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_0_mc_resume()
357 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
359 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
361 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_0_mc_resume()
362 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_0_mc_resume()
365 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
367 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
369 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v2_0_mc_resume()
370 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_mc_resume()
373 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
375 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
377 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
378 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v2_0_mc_resume()
381 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in vcn_v2_0_mc_resume()
502 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
525 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
548 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
576 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
589 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
662 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
685 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
698 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
720 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
734 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
747 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_disable_static_power_gating()
762 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_enable_static_power_gating()
776 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_enable_static_power_gating()
804 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); in vcn_v2_0_start_dpg_mode()
892 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_0_start_dpg_mode()
901 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v2_0_start_dpg_mode()
904 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v2_0_start_dpg_mode()
908 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v2_0_start_dpg_mode()
910 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v2_0_start_dpg_mode()
914 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_0_start_dpg_mode()
916 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v2_0_start_dpg_mode()
919 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_start_dpg_mode()
947 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v2_0_start()
962 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | in vcn_v2_0_start()
972 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); in vcn_v2_0_start()
975 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, in vcn_v2_0_start()
982 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, in vcn_v2_0_start()
989 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, in vcn_v2_0_start()
1007 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); in vcn_v2_0_start()
1015 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in vcn_v2_0_start()
1055 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); in vcn_v2_0_start()
1064 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_0_start()
1068 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v2_0_start()
1070 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v2_0_start()
1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_0_start()
1077 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_start()
1083 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1084 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1085 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_start()
1086 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1087 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_start()
1092 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1093 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1094 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_start()
1095 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1096 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_start()
1160 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); in vcn_v2_0_stop()
1188 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v2_0_stop()
1222 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_0_pause_dpg_mode()
1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
1238 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
1239 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
1240 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
1249 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1251 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1255 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_pause_dpg_mode()
1269 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_0_pause_dpg_mode()
1359 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, in vcn_v2_0_dec_ring_set_wptr()
1366 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_dec_ring_set_wptr()
1598 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
1605 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
1802 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); in vcn_v2_0_start_mmsch()
1803 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); in vcn_v2_0_start_mmsch()
1810 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data); in vcn_v2_0_start_mmsch()
1813 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size); in vcn_v2_0_start_mmsch()
1816 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_0_start_mmsch()
1831 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); in vcn_v2_0_start_mmsch()