549 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
554 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
559 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
565 			amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
569 			amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
1183 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_emit_fence()
1186 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1189 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1192 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1196 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1199 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1202 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1259 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_test_ring()
1324 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));  in uvd_v7_0_ring_emit_ib()
1328 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));  in uvd_v7_0_ring_emit_ib()
1331 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));  in uvd_v7_0_ring_emit_ib()
1334 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));  in uvd_v7_0_ring_emit_ib()
1368 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_wreg()
1371 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_wreg()
1374 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_wreg()
1384 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_reg_wait()
1387 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_reg_wait()
1390 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));  in uvd_v7_0_ring_emit_reg_wait()
1393 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_reg_wait()
1420 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));  in uvd_v7_0_ring_insert_nop()