173 	tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);  in uvd_v5_0_hw_init()
177 	tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v5_0_hw_init()
181 	tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v5_0_hw_init()
186 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v5_0_hw_init()
189 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));  in uvd_v5_0_hw_init()
493 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v5_0_ring_emit_fence()
495 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v5_0_ring_emit_fence()
497 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v5_0_ring_emit_fence()
499 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v5_0_ring_emit_fence()
502 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v5_0_ring_emit_fence()
504 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v5_0_ring_emit_fence()
506 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v5_0_ring_emit_fence()
528 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v5_0_ring_test_ring()
559 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));  in uvd_v5_0_ring_emit_ib()
561 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));  in uvd_v5_0_ring_emit_ib()
563 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));  in uvd_v5_0_ring_emit_ib()
574 		amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));  in uvd_v5_0_ring_insert_nop()