203 	adev->uvd.inst->ring.funcs = &uvd_v3_1_ring_funcs;  in uvd_v3_1_set_ring_funcs()
246 	addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;  in uvd_v3_1_mc_resume()
258 		(AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;  in uvd_v3_1_mc_resume()
263 	addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;  in uvd_v3_1_mc_resume()
267 	addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;  in uvd_v3_1_mc_resume()
285 	uint32_t keysel = adev->uvd.keyselect;  in uvd_v3_1_fw_validate()
322 	struct amdgpu_ring *ring = &adev->uvd.inst->ring;  in uvd_v3_1_start()
517 	amdgpu_fence_process(&adev->uvd.inst->ring);  in uvd_v3_1_process_interrupt()
529 	adev->uvd.inst->irq.num_types = 1;  in uvd_v3_1_set_irq_funcs()
530 	adev->uvd.inst->irq.funcs = &uvd_v3_1_irq_funcs;  in uvd_v3_1_set_irq_funcs()
537 	adev->uvd.num_uvd_inst = 1;  in uvd_v3_1_early_init()
554 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);  in uvd_v3_1_sw_init()
562 	ring = &adev->uvd.inst->ring;  in uvd_v3_1_sw_init()
564 	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,  in uvd_v3_1_sw_init()
574 	ptr = adev->uvd.inst[0].cpu_addr;  in uvd_v3_1_sw_init()
578 	memcpy(&adev->uvd.keyselect, ptr, 4);  in uvd_v3_1_sw_init()
633 	struct amdgpu_ring *ring = &adev->uvd.inst->ring;  in uvd_v3_1_hw_init()
701 	cancel_delayed_work_sync(&adev->uvd.idle_work);  in uvd_v3_1_hw_fini()
725 	cancel_delayed_work_sync(&adev->uvd.idle_work);  in uvd_v3_1_suspend()