1644 	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);  in si_uvd_send_upll_ctlreq()
1649 	WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);  in si_uvd_send_upll_ctlreq()
1661 	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);  in si_uvd_send_upll_ctlreq()
1781 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in si_set_uvd_clocks()
1786 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);  in si_set_uvd_clocks()
1800 	WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);  in si_set_uvd_clocks()
1803 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);  in si_set_uvd_clocks()
1806 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);  in si_set_uvd_clocks()
1809 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in si_set_uvd_clocks()
1818 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);  in si_set_uvd_clocks()
1821 	WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in si_set_uvd_clocks()
1824 	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);  in si_set_uvd_clocks()
1827 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);  in si_set_uvd_clocks()
1830 		WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);  in si_set_uvd_clocks()
1832 		WREG32_P(CG_UPLL_FUNC_CNTL_4,  in si_set_uvd_clocks()
1837 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in si_set_uvd_clocks()
1845 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in si_set_uvd_clocks()
1850 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);  in si_set_uvd_clocks()
1857 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in si_set_uvd_clocks()