116 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_free_microcode()
117 		release_firmware(adev->sdma.instance[i].fw);  in sdma_v2_4_free_microcode()
118 		adev->sdma.instance[i].fw = NULL;  in sdma_v2_4_free_microcode()
149 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_init_microcode()
154 		err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);  in sdma_v2_4_init_microcode()
157 		err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);  in sdma_v2_4_init_microcode()
160 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v2_4_init_microcode()
161 		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);  in sdma_v2_4_init_microcode()
162 		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);  in sdma_v2_4_init_microcode()
163 		if (adev->sdma.instance[i].feature_version >= 20)  in sdma_v2_4_init_microcode()
164 			adev->sdma.instance[i].burst_nop = true;  in sdma_v2_4_init_microcode()
169 			info->fw = adev->sdma.instance[i].fw;  in sdma_v2_4_init_microcode()
179 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_init_microcode()
180 			release_firmware(adev->sdma.instance[i].fw);  in sdma_v2_4_init_microcode()
181 			adev->sdma.instance[i].fw = NULL;  in sdma_v2_4_init_microcode()
231 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v2_4_ring_insert_nop()  local
235 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v2_4_ring_insert_nop()
350 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_gfx_stop()
390 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_enable()
415 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_gfx_resume()
416 		ring = &adev->sdma.instance[i].ring;  in sdma_v2_4_gfx_resume()
480 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_gfx_resume()
481 		ring = &adev->sdma.instance[i].ring;  in sdma_v2_4_gfx_resume()
748 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v2_4_ring_pad_ib()  local
754 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v2_4_ring_pad_ib()
828 	adev->sdma.num_instances = SDMA_MAX_INSTANCE;  in sdma_v2_4_early_init()
846 			      &adev->sdma.trap_irq);  in sdma_v2_4_sw_init()
852 			      &adev->sdma.illegal_inst_irq);  in sdma_v2_4_sw_init()
858 			      &adev->sdma.illegal_inst_irq);  in sdma_v2_4_sw_init()
868 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_sw_init()
869 		ring = &adev->sdma.instance[i].ring;  in sdma_v2_4_sw_init()
873 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,  in sdma_v2_4_sw_init()
889 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v2_4_sw_fini()
890 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v2_4_sw_fini()
1062 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v2_4_process_trap_irq()
1075 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v2_4_process_trap_irq()
1100 		drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);  in sdma_v2_4_process_illegal_inst_irq()
1166 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_set_ring_funcs()
1167 		adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;  in sdma_v2_4_set_ring_funcs()
1168 		adev->sdma.instance[i].ring.me = i;  in sdma_v2_4_set_ring_funcs()
1183 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;  in sdma_v2_4_set_irq_funcs()
1184 	adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;  in sdma_v2_4_set_irq_funcs()
1185 	adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;  in sdma_v2_4_set_irq_funcs()
1252 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v2_4_set_buffer_funcs()
1268 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v2_4_set_vm_pte_funcs()
1270 			&adev->sdma.instance[i].ring.sched;  in sdma_v2_4_set_vm_pte_funcs()
1272 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in sdma_v2_4_set_vm_pte_funcs()