765 	struct v11_compute_mqd *mqd = ring->mqd_ptr;  in mes_v11_0_mqd_init()  local
769 	mqd->header = 0xC0310800;  in mes_v11_0_mqd_init()
770 	mqd->compute_pipelinestat_enable = 0x00000001;  in mes_v11_0_mqd_init()
771 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in mes_v11_0_mqd_init()
772 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in mes_v11_0_mqd_init()
773 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in mes_v11_0_mqd_init()
774 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in mes_v11_0_mqd_init()
775 	mqd->compute_misc_reserved = 0x00000007;  in mes_v11_0_mqd_init()
784 	mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);  in mes_v11_0_mqd_init()
785 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);  in mes_v11_0_mqd_init()
786 	mqd->cp_hqd_eop_control = tmp;  in mes_v11_0_mqd_init()
790 	mqd->cp_hqd_pq_rptr = 0;  in mes_v11_0_mqd_init()
791 	mqd->cp_hqd_pq_wptr_lo = 0;  in mes_v11_0_mqd_init()
792 	mqd->cp_hqd_pq_wptr_hi = 0;  in mes_v11_0_mqd_init()
795 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;  in mes_v11_0_mqd_init()
796 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);  in mes_v11_0_mqd_init()
801 	mqd->cp_mqd_control = tmp;  in mes_v11_0_mqd_init()
805 	mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);  in mes_v11_0_mqd_init()
806 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in mes_v11_0_mqd_init()
810 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in mes_v11_0_mqd_init()
811 	mqd->cp_hqd_pq_rptr_report_addr_hi =  in mes_v11_0_mqd_init()
816 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;  in mes_v11_0_mqd_init()
817 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in mes_v11_0_mqd_init()
830 	mqd->cp_hqd_pq_control = tmp;  in mes_v11_0_mqd_init()
847 	mqd->cp_hqd_pq_doorbell_control = tmp;  in mes_v11_0_mqd_init()
849 	mqd->cp_hqd_vmid = 0;  in mes_v11_0_mqd_init()
851 	mqd->cp_hqd_active = 1;  in mes_v11_0_mqd_init()
856 	mqd->cp_hqd_persistent_state = tmp;  in mes_v11_0_mqd_init()
858 	mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;  in mes_v11_0_mqd_init()
859 	mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;  in mes_v11_0_mqd_init()
860 	mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;  in mes_v11_0_mqd_init()
867 	struct v11_compute_mqd *mqd = ring->mqd_ptr;  in mes_v11_0_queue_init_register()  local
886 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);  in mes_v11_0_queue_init_register()
887 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);  in mes_v11_0_queue_init_register()
895 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);  in mes_v11_0_queue_init_register()
896 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);  in mes_v11_0_queue_init_register()
900 		     mqd->cp_hqd_pq_rptr_report_addr_lo);  in mes_v11_0_queue_init_register()
902 		     mqd->cp_hqd_pq_rptr_report_addr_hi);  in mes_v11_0_queue_init_register()
905 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);  in mes_v11_0_queue_init_register()
909 		     mqd->cp_hqd_pq_wptr_poll_addr_lo);  in mes_v11_0_queue_init_register()
911 		     mqd->cp_hqd_pq_wptr_poll_addr_hi);  in mes_v11_0_queue_init_register()
915 		     mqd->cp_hqd_pq_doorbell_control);  in mes_v11_0_queue_init_register()
918 	WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);  in mes_v11_0_queue_init_register()
921 	WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);  in mes_v11_0_queue_init_register()