200 	u32 tmp;  in gmc_v8_0_mc_resume()  local
203 	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v8_0_mc_resume()
204 	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);  in gmc_v8_0_mc_resume()
205 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v8_0_mc_resume()
207 	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);  in gmc_v8_0_mc_resume()
208 	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);  in gmc_v8_0_mc_resume()
209 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v8_0_mc_resume()
444 	u32 tmp;  in gmc_v8_0_mc_program()  local
462 		tmp = RREG32(mmVGA_HDP_CONTROL);  in gmc_v8_0_mc_program()
463 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);  in gmc_v8_0_mc_program()
464 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v8_0_mc_program()
467 		tmp = RREG32(mmVGA_RENDER_CONTROL);  in gmc_v8_0_mc_program()
468 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);  in gmc_v8_0_mc_program()
469 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v8_0_mc_program()
480 		tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;  in gmc_v8_0_mc_program()
481 		tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);  in gmc_v8_0_mc_program()
482 		WREG32(mmMC_VM_FB_LOCATION, tmp);  in gmc_v8_0_mc_program()
498 	tmp = RREG32(mmHDP_MISC_CNTL);  in gmc_v8_0_mc_program()
499 	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);  in gmc_v8_0_mc_program()
500 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v8_0_mc_program()
502 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v8_0_mc_program()
503 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v8_0_mc_program()
518 	u32 tmp;  in gmc_v8_0_mc_init()  local
525 		tmp = RREG32(mmMC_ARB_RAMCFG);  in gmc_v8_0_mc_init()
526 		if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {  in gmc_v8_0_mc_init()
531 		tmp = RREG32(mmMC_SHARED_CHMAP);  in gmc_v8_0_mc_init()
532 		switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {  in gmc_v8_0_mc_init()
565 	tmp = RREG32(mmCONFIG_MEMSIZE);  in gmc_v8_0_mc_init()
567 	if (tmp & 0xffff0000) {  in gmc_v8_0_mc_init()
568 		DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);  in gmc_v8_0_mc_init()
569 		if (tmp & 0xffff)  in gmc_v8_0_mc_init()
570 			tmp &= 0xffff;  in gmc_v8_0_mc_init()
572 	adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;  in gmc_v8_0_mc_init()
637 	unsigned int tmp;  in gmc_v8_0_flush_gpu_tlb_pasid()  local
644 		tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);  in gmc_v8_0_flush_gpu_tlb_pasid()
645 		if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&  in gmc_v8_0_flush_gpu_tlb_pasid()
646 			(tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {  in gmc_v8_0_flush_gpu_tlb_pasid()
749 	u32 tmp;  in gmc_v8_0_set_fault_enable_default()  local
751 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v8_0_set_fault_enable_default()
752 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v8_0_set_fault_enable_default()
754 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v8_0_set_fault_enable_default()
756 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v8_0_set_fault_enable_default()
758 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v8_0_set_fault_enable_default()
760 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v8_0_set_fault_enable_default()
762 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v8_0_set_fault_enable_default()
764 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v8_0_set_fault_enable_default()
766 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_set_fault_enable_default()
777 	u32 tmp;  in gmc_v8_0_set_prt()  local
784 	tmp = RREG32(mmVM_PRT_CNTL);  in gmc_v8_0_set_prt()
785 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v8_0_set_prt()
787 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v8_0_set_prt()
789 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v8_0_set_prt()
791 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v8_0_set_prt()
793 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v8_0_set_prt()
795 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v8_0_set_prt()
797 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v8_0_set_prt()
799 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v8_0_set_prt()
840 	u32 tmp, field;  in gmc_v8_0_gart_enable()  local
851 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v8_0_gart_enable()
852 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gmc_v8_0_gart_enable()
853 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);  in gmc_v8_0_gart_enable()
854 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gmc_v8_0_gart_enable()
855 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);  in gmc_v8_0_gart_enable()
856 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);  in gmc_v8_0_gart_enable()
857 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_enable()
859 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v8_0_gart_enable()
860 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gmc_v8_0_gart_enable()
861 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gmc_v8_0_gart_enable()
862 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);  in gmc_v8_0_gart_enable()
863 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);  in gmc_v8_0_gart_enable()
864 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);  in gmc_v8_0_gart_enable()
865 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gmc_v8_0_gart_enable()
866 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);  in gmc_v8_0_gart_enable()
867 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_enable()
868 	tmp = RREG32(mmVM_L2_CNTL2);  in gmc_v8_0_gart_enable()
869 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gmc_v8_0_gart_enable()
870 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gmc_v8_0_gart_enable()
871 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v8_0_gart_enable()
874 	tmp = RREG32(mmVM_L2_CNTL3);  in gmc_v8_0_gart_enable()
875 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);  in gmc_v8_0_gart_enable()
876 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);  in gmc_v8_0_gart_enable()
877 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);  in gmc_v8_0_gart_enable()
878 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v8_0_gart_enable()
880 	tmp = RREG32(mmVM_L2_CNTL4);  in gmc_v8_0_gart_enable()
881 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);  in gmc_v8_0_gart_enable()
882 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);  in gmc_v8_0_gart_enable()
883 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);  in gmc_v8_0_gart_enable()
884 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);  in gmc_v8_0_gart_enable()
885 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);  in gmc_v8_0_gart_enable()
886 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);  in gmc_v8_0_gart_enable()
887 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);  in gmc_v8_0_gart_enable()
888 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);  in gmc_v8_0_gart_enable()
889 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);  in gmc_v8_0_gart_enable()
890 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);  in gmc_v8_0_gart_enable()
891 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);  in gmc_v8_0_gart_enable()
892 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);  in gmc_v8_0_gart_enable()
893 	WREG32(mmVM_L2_CNTL4, tmp);  in gmc_v8_0_gart_enable()
901 	tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v8_0_gart_enable()
902 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gmc_v8_0_gart_enable()
903 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gmc_v8_0_gart_enable()
904 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v8_0_gart_enable()
905 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_gart_enable()
931 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v8_0_gart_enable()
932 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gmc_v8_0_gart_enable()
933 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);  in gmc_v8_0_gart_enable()
934 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v8_0_gart_enable()
935 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v8_0_gart_enable()
936 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v8_0_gart_enable()
937 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v8_0_gart_enable()
938 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v8_0_gart_enable()
939 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v8_0_gart_enable()
940 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v8_0_gart_enable()
941 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,  in gmc_v8_0_gart_enable()
943 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_gart_enable()
982 	u32 tmp;  in gmc_v8_0_gart_disable()  local
988 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v8_0_gart_disable()
989 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gmc_v8_0_gart_disable()
990 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);  in gmc_v8_0_gart_disable()
991 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);  in gmc_v8_0_gart_disable()
992 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_disable()
994 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v8_0_gart_disable()
995 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);  in gmc_v8_0_gart_disable()
996 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_disable()
1110 		u32 tmp;  in gmc_v8_0_sw_init()  local
1114 			tmp = RREG32(mmMC_SEQ_MISC0_FIJI);  in gmc_v8_0_sw_init()
1116 			tmp = RREG32(mmMC_SEQ_MISC0);  in gmc_v8_0_sw_init()
1117 		tmp &= MC_SEQ_MISC0__MT__MASK;  in gmc_v8_0_sw_init()
1118 		adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);  in gmc_v8_0_sw_init()
1180 		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);  in gmc_v8_0_sw_init()  local
1182 		tmp <<= 22;  in gmc_v8_0_sw_init()
1183 		adev->vm_manager.vram_base_offset = tmp;  in gmc_v8_0_sw_init()
1283 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v8_0_is_idle()  local
1285 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in gmc_v8_0_is_idle()
1295 	u32 tmp;  in gmc_v8_0_wait_for_idle()  local
1300 		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |  in gmc_v8_0_wait_for_idle()
1306 		if (!tmp)  in gmc_v8_0_wait_for_idle()
1318 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v8_0_check_soft_reset()  local
1320 	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)  in gmc_v8_0_check_soft_reset()
1324 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in gmc_v8_0_check_soft_reset()
1364 		u32 tmp;  in gmc_v8_0_soft_reset()  local
1366 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v8_0_soft_reset()
1367 		tmp |= srbm_soft_reset;  in gmc_v8_0_soft_reset()
1368 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in gmc_v8_0_soft_reset()
1369 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1370 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v8_0_soft_reset()
1374 		tmp &= ~srbm_soft_reset;  in gmc_v8_0_soft_reset()
1375 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1376 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v8_0_soft_reset()
1401 	u32 tmp;  in gmc_v8_0_vm_fault_interrupt_state()  local
1413 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v8_0_vm_fault_interrupt_state()
1414 		tmp &= ~bits;  in gmc_v8_0_vm_fault_interrupt_state()
1415 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1417 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v8_0_vm_fault_interrupt_state()
1418 		tmp &= ~bits;  in gmc_v8_0_vm_fault_interrupt_state()
1419 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1423 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v8_0_vm_fault_interrupt_state()
1424 		tmp |= bits;  in gmc_v8_0_vm_fault_interrupt_state()
1425 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1427 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v8_0_vm_fault_interrupt_state()
1428 		tmp |= bits;  in gmc_v8_0_vm_fault_interrupt_state()
1429 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()