189 	uint32_t tmp;  in gfxhub_v3_0_3_init_tlb_regs()  local
192 	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v3_0_3_init_tlb_regs()
194 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v3_0_3_init_tlb_regs()
195 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v3_0_3_init_tlb_regs()
196 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v3_0_3_init_tlb_regs()
198 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v3_0_3_init_tlb_regs()
200 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);  in gfxhub_v3_0_3_init_tlb_regs()
201 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v3_0_3_init_tlb_regs()
204 	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v3_0_3_init_tlb_regs()
209 	uint32_t tmp;  in gfxhub_v3_0_3_init_cache_regs()  local
218 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);  in gfxhub_v3_0_3_init_cache_regs()
219 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v3_0_3_init_cache_regs()
220 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);  in gfxhub_v3_0_3_init_cache_regs()
221 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v3_0_3_init_cache_regs()
224 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v3_0_3_init_cache_regs()
226 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v3_0_3_init_cache_regs()
227 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v3_0_3_init_cache_regs()
228 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v3_0_3_init_cache_regs()
229 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);  in gfxhub_v3_0_3_init_cache_regs()
231 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);  in gfxhub_v3_0_3_init_cache_regs()
232 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v3_0_3_init_cache_regs()
233 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v3_0_3_init_cache_regs()
234 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);  in gfxhub_v3_0_3_init_cache_regs()
236 	tmp = regGCVM_L2_CNTL3_DEFAULT;  in gfxhub_v3_0_3_init_cache_regs()
238 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v3_0_3_init_cache_regs()
239 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v3_0_3_init_cache_regs()
242 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v3_0_3_init_cache_regs()
243 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v3_0_3_init_cache_regs()
246 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);  in gfxhub_v3_0_3_init_cache_regs()
248 	tmp = regGCVM_L2_CNTL4_DEFAULT;  in gfxhub_v3_0_3_init_cache_regs()
249 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v3_0_3_init_cache_regs()
250 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v3_0_3_init_cache_regs()
251 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);  in gfxhub_v3_0_3_init_cache_regs()
253 	tmp = regGCVM_L2_CNTL5_DEFAULT;  in gfxhub_v3_0_3_init_cache_regs()
254 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);  in gfxhub_v3_0_3_init_cache_regs()
255 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);  in gfxhub_v3_0_3_init_cache_regs()
260 	uint32_t tmp;  in gfxhub_v3_0_3_enable_system_domain()  local
262 	tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);  in gfxhub_v3_0_3_enable_system_domain()
263 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v3_0_3_enable_system_domain()
264 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gfxhub_v3_0_3_enable_system_domain()
265 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,  in gfxhub_v3_0_3_enable_system_domain()
267 	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);  in gfxhub_v3_0_3_enable_system_domain()
297 	uint32_t tmp;  in gfxhub_v3_0_3_setup_vmid_config()  local
300 		tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);  in gfxhub_v3_0_3_setup_vmid_config()
301 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v3_0_3_setup_vmid_config()
302 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v3_0_3_setup_vmid_config()
304 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
306 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
308 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
310 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
312 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
314 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
316 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
318 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
322 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v3_0_3_setup_vmid_config()
326 				    i * hub->ctx_distance, tmp);  in gfxhub_v3_0_3_setup_vmid_config()
339 	hub->vm_cntx_cntl = tmp;  in gfxhub_v3_0_3_setup_vmid_config()
386 	u32 tmp;  in gfxhub_v3_0_3_gart_disable()  local
395 	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v3_0_3_gart_disable()
396 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v3_0_3_gart_disable()
397 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v3_0_3_gart_disable()
399 	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v3_0_3_gart_disable()
415 	u32 tmp;  in gfxhub_v3_0_3_set_fault_enable_default()  local
423 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v3_0_3_set_fault_enable_default()
424 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
426 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
428 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
430 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
432 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
435 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
437 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
439 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
441 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
443 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
445 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
448 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
450 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v3_0_3_set_fault_enable_default()
453 	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v3_0_3_set_fault_enable_default()