154 	uint32_t tmp;  in gfxhub_v1_0_init_tlb_regs()  local
157 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_init_tlb_regs()
159 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v1_0_init_tlb_regs()
160 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v1_0_init_tlb_regs()
161 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
163 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
165 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
167 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);  in gfxhub_v1_0_init_tlb_regs()
169 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_init_tlb_regs()
174 	uint32_t tmp;  in gfxhub_v1_0_init_cache_regs()  local
177 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);  in gfxhub_v1_0_init_cache_regs()
178 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
179 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gfxhub_v1_0_init_cache_regs()
181 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,  in gfxhub_v1_0_init_cache_regs()
183 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v1_0_init_cache_regs()
184 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v1_0_init_cache_regs()
185 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v1_0_init_cache_regs()
186 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);  in gfxhub_v1_0_init_cache_regs()
188 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);  in gfxhub_v1_0_init_cache_regs()
189 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v1_0_init_cache_regs()
190 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
191 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);  in gfxhub_v1_0_init_cache_regs()
193 	tmp = mmVM_L2_CNTL3_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
195 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v1_0_init_cache_regs()
196 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
199 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v1_0_init_cache_regs()
200 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
203 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);  in gfxhub_v1_0_init_cache_regs()
205 	tmp = mmVM_L2_CNTL4_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
207 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);  in gfxhub_v1_0_init_cache_regs()
208 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);  in gfxhub_v1_0_init_cache_regs()
210 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
211 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
213 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);  in gfxhub_v1_0_init_cache_regs()
218 	uint32_t tmp;  in gfxhub_v1_0_enable_system_domain()  local
220 	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);  in gfxhub_v1_0_enable_system_domain()
221 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_enable_system_domain()
222 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v1_0_enable_system_domain()
224 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,  in gfxhub_v1_0_enable_system_domain()
226 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,  in gfxhub_v1_0_enable_system_domain()
228 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);  in gfxhub_v1_0_enable_system_domain()
252 	uint32_t tmp;  in gfxhub_v1_0_setup_vmid_config()  local
263 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);  in gfxhub_v1_0_setup_vmid_config()
264 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_setup_vmid_config()
265 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v1_0_setup_vmid_config()
267 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
269 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
272 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
274 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
276 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
278 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
280 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
282 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
289 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
294 				    i * hub->ctx_distance, tmp);  in gfxhub_v1_0_setup_vmid_config()
342 	u32 tmp;  in gfxhub_v1_0_gart_disable()  local
355 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_gart_disable()
356 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v1_0_gart_disable()
357 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_gart_disable()
361 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_gart_disable()
377 	u32 tmp;  in gfxhub_v1_0_set_fault_enable_default()  local
378 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v1_0_set_fault_enable_default()
379 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
381 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
383 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
385 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
387 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_set_fault_enable_default()
391 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
393 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
395 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
397 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
399 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
401 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
404 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
406 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
409 	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v1_0_set_fault_enable_default()