5219 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad…  in wave_read_ind()  argument
5223 		(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |  in wave_read_ind()
5229 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,  in wave_read_regs()  argument
5235 		(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |  in wave_read_regs()
5244 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3…  in gfx_v8_0_read_wave_data()  argument
5248 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);  in gfx_v8_0_read_wave_data()
5249 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);  in gfx_v8_0_read_wave_data()
5250 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);  in gfx_v8_0_read_wave_data()
5251 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);  in gfx_v8_0_read_wave_data()
5252 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);  in gfx_v8_0_read_wave_data()
5253 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);  in gfx_v8_0_read_wave_data()
5254 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);  in gfx_v8_0_read_wave_data()
5255 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);  in gfx_v8_0_read_wave_data()
5256 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);  in gfx_v8_0_read_wave_data()
5257 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);  in gfx_v8_0_read_wave_data()
5258 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);  in gfx_v8_0_read_wave_data()
5259 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);  in gfx_v8_0_read_wave_data()
5260 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);  in gfx_v8_0_read_wave_data()
5261 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);  in gfx_v8_0_read_wave_data()
5262 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);  in gfx_v8_0_read_wave_data()
5263 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);  in gfx_v8_0_read_wave_data()
5264 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);  in gfx_v8_0_read_wave_data()
5265 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);  in gfx_v8_0_read_wave_data()
5266 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);  in gfx_v8_0_read_wave_data()
5269 static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,  in gfx_v8_0_read_wave_sgprs()  argument
5274 		adev, simd, wave, 0,  in gfx_v8_0_read_wave_sgprs()