Lines Matching refs:mqd
3524 struct v11_gfx_mqd *mqd = m; in gfx_v11_0_gfx_mqd_init() local
3530 mqd->cp_gfx_hqd_wptr = 0; in gfx_v11_0_gfx_mqd_init()
3531 mqd->cp_gfx_hqd_wptr_hi = 0; in gfx_v11_0_gfx_mqd_init()
3534 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3535 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v11_0_gfx_mqd_init()
3542 mqd->cp_gfx_mqd_control = tmp; in gfx_v11_0_gfx_mqd_init()
3547 mqd->cp_gfx_hqd_vmid = 0; in gfx_v11_0_gfx_mqd_init()
3553 mqd->cp_gfx_hqd_queue_priority = tmp; in gfx_v11_0_gfx_mqd_init()
3558 mqd->cp_gfx_hqd_quantum = tmp; in gfx_v11_0_gfx_mqd_init()
3562 mqd->cp_gfx_hqd_base = hqd_gpu_addr; in gfx_v11_0_gfx_mqd_init()
3563 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v11_0_gfx_mqd_init()
3567 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3568 mqd->cp_gfx_hqd_rptr_addr_hi = in gfx_v11_0_gfx_mqd_init()
3573 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3574 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
3584 mqd->cp_gfx_hqd_cntl = tmp; in gfx_v11_0_gfx_mqd_init()
3596 mqd->cp_rb_doorbell_control = tmp; in gfx_v11_0_gfx_mqd_init()
3599 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); in gfx_v11_0_gfx_mqd_init()
3602 mqd->cp_gfx_hqd_active = 1; in gfx_v11_0_gfx_mqd_init()
3611 struct v11_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_gfx_queue_init_register() local
3614 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); in gfx_v11_0_gfx_queue_init_register()
3615 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); in gfx_v11_0_gfx_queue_init_register()
3618 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); in gfx_v11_0_gfx_queue_init_register()
3619 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in gfx_v11_0_gfx_queue_init_register()
3622 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); in gfx_v11_0_gfx_queue_init_register()
3625 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); in gfx_v11_0_gfx_queue_init_register()
3628 mqd->cp_gfx_hqd_queue_priority); in gfx_v11_0_gfx_queue_init_register()
3629 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); in gfx_v11_0_gfx_queue_init_register()
3632 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); in gfx_v11_0_gfx_queue_init_register()
3633 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); in gfx_v11_0_gfx_queue_init_register()
3636 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); in gfx_v11_0_gfx_queue_init_register()
3637 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); in gfx_v11_0_gfx_queue_init_register()
3640 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); in gfx_v11_0_gfx_queue_init_register()
3643 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); in gfx_v11_0_gfx_queue_init_register()
3644 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); in gfx_v11_0_gfx_queue_init_register()
3647 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); in gfx_v11_0_gfx_queue_init_register()
3650 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); in gfx_v11_0_gfx_queue_init_register()
3659 struct v11_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_gfx_init_queue() local
3663 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3673 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3677 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3762 struct v11_compute_mqd *mqd = m; in gfx_v11_0_compute_mqd_init() local
3766 mqd->header = 0xC0310800; in gfx_v11_0_compute_mqd_init()
3767 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v11_0_compute_mqd_init()
3768 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
3769 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
3770 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
3771 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
3772 mqd->compute_misc_reserved = 0x00000007; in gfx_v11_0_compute_mqd_init()
3775 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; in gfx_v11_0_compute_mqd_init()
3776 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in gfx_v11_0_compute_mqd_init()
3783 mqd->cp_hqd_eop_control = tmp; in gfx_v11_0_compute_mqd_init()
3802 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v11_0_compute_mqd_init()
3805 mqd->cp_hqd_dequeue_request = 0; in gfx_v11_0_compute_mqd_init()
3806 mqd->cp_hqd_pq_rptr = 0; in gfx_v11_0_compute_mqd_init()
3807 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v11_0_compute_mqd_init()
3808 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v11_0_compute_mqd_init()
3811 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
3812 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v11_0_compute_mqd_init()
3817 mqd->cp_mqd_control = tmp; in gfx_v11_0_compute_mqd_init()
3821 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v11_0_compute_mqd_init()
3822 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v11_0_compute_mqd_init()
3834 mqd->cp_hqd_pq_control = tmp; in gfx_v11_0_compute_mqd_init()
3838 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
3839 mqd->cp_hqd_pq_rptr_report_addr_hi = in gfx_v11_0_compute_mqd_init()
3844 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
3845 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
3862 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v11_0_compute_mqd_init()
3865 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); in gfx_v11_0_compute_mqd_init()
3868 mqd->cp_hqd_vmid = 0; in gfx_v11_0_compute_mqd_init()
3872 mqd->cp_hqd_persistent_state = tmp; in gfx_v11_0_compute_mqd_init()
3877 mqd->cp_hqd_ib_control = tmp; in gfx_v11_0_compute_mqd_init()
3880 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; in gfx_v11_0_compute_mqd_init()
3881 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; in gfx_v11_0_compute_mqd_init()
3883 mqd->cp_hqd_active = prop->hqd_active; in gfx_v11_0_compute_mqd_init()
3891 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kiq_init_register() local
3903 mqd->cp_hqd_eop_base_addr_lo); in gfx_v11_0_kiq_init_register()
3905 mqd->cp_hqd_eop_base_addr_hi); in gfx_v11_0_kiq_init_register()
3909 mqd->cp_hqd_eop_control); in gfx_v11_0_kiq_init_register()
3913 mqd->cp_hqd_pq_doorbell_control); in gfx_v11_0_kiq_init_register()
3924 mqd->cp_hqd_dequeue_request); in gfx_v11_0_kiq_init_register()
3926 mqd->cp_hqd_pq_rptr); in gfx_v11_0_kiq_init_register()
3928 mqd->cp_hqd_pq_wptr_lo); in gfx_v11_0_kiq_init_register()
3930 mqd->cp_hqd_pq_wptr_hi); in gfx_v11_0_kiq_init_register()
3935 mqd->cp_mqd_base_addr_lo); in gfx_v11_0_kiq_init_register()
3937 mqd->cp_mqd_base_addr_hi); in gfx_v11_0_kiq_init_register()
3941 mqd->cp_mqd_control); in gfx_v11_0_kiq_init_register()
3945 mqd->cp_hqd_pq_base_lo); in gfx_v11_0_kiq_init_register()
3947 mqd->cp_hqd_pq_base_hi); in gfx_v11_0_kiq_init_register()
3951 mqd->cp_hqd_pq_control); in gfx_v11_0_kiq_init_register()
3955 mqd->cp_hqd_pq_rptr_report_addr_lo); in gfx_v11_0_kiq_init_register()
3957 mqd->cp_hqd_pq_rptr_report_addr_hi); in gfx_v11_0_kiq_init_register()
3961 mqd->cp_hqd_pq_wptr_poll_addr_lo); in gfx_v11_0_kiq_init_register()
3963 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v11_0_kiq_init_register()
3974 mqd->cp_hqd_pq_doorbell_control); in gfx_v11_0_kiq_init_register()
3978 mqd->cp_hqd_pq_wptr_lo); in gfx_v11_0_kiq_init_register()
3980 mqd->cp_hqd_pq_wptr_hi); in gfx_v11_0_kiq_init_register()
3983 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v11_0_kiq_init_register()
3986 mqd->cp_hqd_persistent_state); in gfx_v11_0_kiq_init_register()
3990 mqd->cp_hqd_active); in gfx_v11_0_kiq_init_register()
4001 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kiq_init_queue() local
4009 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4021 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4030 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4039 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kcq_init_queue() local
4043 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4051 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4055 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()