187 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v8_0_page_flip()  local
188 	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;  in dce_v8_0_page_flip()
191 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?  in dce_v8_0_page_flip()
194 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
197 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
200 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
203 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v8_0_page_flip()
450 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_program_fmt()  local
515 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_fmt()
533 				       struct amdgpu_crtc *amdgpu_crtc,  in dce_v8_0_line_buffer_adjust()  argument
537 	u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;  in dce_v8_0_line_buffer_adjust()
546 	if (amdgpu_crtc->base.enabled && mode) {  in dce_v8_0_line_buffer_adjust()
566 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,  in dce_v8_0_line_buffer_adjust()
579 	if (amdgpu_crtc->base.enabled && mode) {  in dce_v8_0_line_buffer_adjust()
963 					struct amdgpu_crtc *amdgpu_crtc,  in dce_v8_0_program_watermarks()  argument
966 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;  in dce_v8_0_program_watermarks()
973 	if (amdgpu_crtc->base.enabled && num_heads && mode) {  in dce_v8_0_program_watermarks()
998 		wm_high.vsc = amdgpu_crtc->vsc;  in dce_v8_0_program_watermarks()
1000 		if (amdgpu_crtc->rmx_type != RMX_OFF)  in dce_v8_0_program_watermarks()
1037 		wm_low.vsc = amdgpu_crtc->vsc;  in dce_v8_0_program_watermarks()
1039 		if (amdgpu_crtc->rmx_type != RMX_OFF)  in dce_v8_0_program_watermarks()
1061 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_program_watermarks()
1065 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_watermarks()
1066 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_program_watermarks()
1070 	tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_program_watermarks()
1073 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_watermarks()
1074 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_program_watermarks()
1078 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);  in dce_v8_0_program_watermarks()
1081 	amdgpu_crtc->line_time = line_time;  in dce_v8_0_program_watermarks()
1082 	amdgpu_crtc->wm_high = latency_watermark_a;  in dce_v8_0_program_watermarks()
1083 	amdgpu_crtc->wm_low = latency_watermark_b;  in dce_v8_0_program_watermarks()
1085 	amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;  in dce_v8_0_program_watermarks()
1496 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_audio_set_dto()  local
1508 …WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SO…  in dce_v8_0_audio_set_dto()
1541 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_afmt_setmode()  local
1542 		bpc = amdgpu_crtc->bpc;  in dce_v8_0_afmt_setmode()
1753 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_vga_enable()  local
1758 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;  in dce_v8_0_vga_enable()
1760 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);  in dce_v8_0_vga_enable()
1762 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);  in dce_v8_0_vga_enable()
1767 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_grph_enable()  local
1772 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);  in dce_v8_0_grph_enable()
1774 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_grph_enable()
1781 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_do_set_base()  local
1936 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1938 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1940 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1942 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1944 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1946 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v8_0_crtc_do_set_base()
1947 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v8_0_crtc_do_set_base()
1954 	WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1961 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1962 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1963 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1964 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1965 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v8_0_crtc_do_set_base()
1966 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v8_0_crtc_do_set_base()
1969 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v8_0_crtc_do_set_base()
1973 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1978 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1982 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1986 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
2008 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_set_interleave()  local
2011 		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,  in dce_v8_0_set_interleave()
2014 		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_set_interleave()
2019 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_load_lut()  local
2025 	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);  in dce_v8_0_crtc_load_lut()
2027 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2030 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2032 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2034 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2038 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2040 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2041 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2042 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2044 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2045 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2046 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2048 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2049 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v8_0_crtc_load_lut()
2051 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2056 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2062 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2066 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2069 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2072 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2076 	WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2080 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2137 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_pick_pll()  local
2143 	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {  in dce_v8_0_pick_pll()
2188 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_lock_cursor()  local
2191 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v8_0_lock_cursor()
2196 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v8_0_lock_cursor()
2201 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_hide_cursor()  local
2204 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_hide_cursor()
2211 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_show_cursor()  local
2214 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2215 	       upper_32_bits(amdgpu_crtc->cursor_addr));  in dce_v8_0_show_cursor()
2216 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2217 	       lower_32_bits(amdgpu_crtc->cursor_addr));  in dce_v8_0_show_cursor()
2219 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2228 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_cursor_move_locked()  local
2232 	amdgpu_crtc->cursor_x = x;  in dce_v8_0_cursor_move_locked()
2233 	amdgpu_crtc->cursor_y = y;  in dce_v8_0_cursor_move_locked()
2241 		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);  in dce_v8_0_cursor_move_locked()
2245 		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);  in dce_v8_0_cursor_move_locked()
2249 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v8_0_cursor_move_locked()
2250 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v8_0_cursor_move_locked()
2251 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v8_0_cursor_move_locked()
2252 	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));  in dce_v8_0_cursor_move_locked()
2277 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_cursor_set2()  local
2289 	if ((width > amdgpu_crtc->max_cursor_width) ||  in dce_v8_0_crtc_cursor_set2()
2290 	    (height > amdgpu_crtc->max_cursor_height)) {  in dce_v8_0_crtc_cursor_set2()
2297 		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);  in dce_v8_0_crtc_cursor_set2()
2315 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);  in dce_v8_0_crtc_cursor_set2()
2319 	if (width != amdgpu_crtc->cursor_width ||  in dce_v8_0_crtc_cursor_set2()
2320 	    height != amdgpu_crtc->cursor_height ||  in dce_v8_0_crtc_cursor_set2()
2321 	    hot_x != amdgpu_crtc->cursor_hot_x ||  in dce_v8_0_crtc_cursor_set2()
2322 	    hot_y != amdgpu_crtc->cursor_hot_y) {  in dce_v8_0_crtc_cursor_set2()
2325 		x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;  in dce_v8_0_crtc_cursor_set2()
2326 		y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;  in dce_v8_0_crtc_cursor_set2()
2330 		amdgpu_crtc->cursor_width = width;  in dce_v8_0_crtc_cursor_set2()
2331 		amdgpu_crtc->cursor_height = height;  in dce_v8_0_crtc_cursor_set2()
2332 		amdgpu_crtc->cursor_hot_x = hot_x;  in dce_v8_0_crtc_cursor_set2()
2333 		amdgpu_crtc->cursor_hot_y = hot_y;  in dce_v8_0_crtc_cursor_set2()
2340 	if (amdgpu_crtc->cursor_bo) {  in dce_v8_0_crtc_cursor_set2()
2341 		struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);  in dce_v8_0_crtc_cursor_set2()
2347 		drm_gem_object_put(amdgpu_crtc->cursor_bo);  in dce_v8_0_crtc_cursor_set2()
2350 	amdgpu_crtc->cursor_bo = obj;  in dce_v8_0_crtc_cursor_set2()
2356 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_cursor_reset()  local
2358 	if (amdgpu_crtc->cursor_bo) {  in dce_v8_0_cursor_reset()
2361 		dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,  in dce_v8_0_cursor_reset()
2362 					    amdgpu_crtc->cursor_y);  in dce_v8_0_cursor_reset()
2381 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_destroy()  local
2384 	kfree(amdgpu_crtc);  in dce_v8_0_crtc_destroy()
2404 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_dpms()  local
2409 		amdgpu_crtc->enabled = true;  in dce_v8_0_crtc_dpms()
2416 						amdgpu_crtc->crtc_id);  in dce_v8_0_crtc_dpms()
2426 		if (amdgpu_crtc->enabled) {  in dce_v8_0_crtc_dpms()
2432 		amdgpu_crtc->enabled = false;  in dce_v8_0_crtc_dpms()
2455 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_disable()  local
2483 		    i != amdgpu_crtc->crtc_id &&  in dce_v8_0_crtc_disable()
2484 		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {  in dce_v8_0_crtc_disable()
2492 	switch (amdgpu_crtc->pll_id) {  in dce_v8_0_crtc_disable()
2496 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,  in dce_v8_0_crtc_disable()
2504 			amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,  in dce_v8_0_crtc_disable()
2511 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;  in dce_v8_0_crtc_disable()
2512 	amdgpu_crtc->adjusted_clock = 0;  in dce_v8_0_crtc_disable()
2513 	amdgpu_crtc->encoder = NULL;  in dce_v8_0_crtc_disable()
2514 	amdgpu_crtc->connector = NULL;  in dce_v8_0_crtc_disable()
2522 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_mode_set()  local
2524 	if (!amdgpu_crtc->adjusted_clock)  in dce_v8_0_crtc_mode_set()
2534 	amdgpu_crtc->hw_mode = *adjusted_mode;  in dce_v8_0_crtc_mode_set()
2543 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_mode_fixup()  local
2550 			amdgpu_crtc->encoder = encoder;  in dce_v8_0_crtc_mode_fixup()
2551 			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);  in dce_v8_0_crtc_mode_fixup()
2555 	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {  in dce_v8_0_crtc_mode_fixup()
2556 		amdgpu_crtc->encoder = NULL;  in dce_v8_0_crtc_mode_fixup()
2557 		amdgpu_crtc->connector = NULL;  in dce_v8_0_crtc_mode_fixup()
2565 	amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);  in dce_v8_0_crtc_mode_fixup()
2567 	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&  in dce_v8_0_crtc_mode_fixup()
2568 	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))  in dce_v8_0_crtc_mode_fixup()
2601 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v8_0_crtc_init()  local
2603 	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +  in dce_v8_0_crtc_init()
2605 	if (amdgpu_crtc == NULL)  in dce_v8_0_crtc_init()
2608 	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);  in dce_v8_0_crtc_init()
2610 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);  in dce_v8_0_crtc_init()
2611 	amdgpu_crtc->crtc_id = index;  in dce_v8_0_crtc_init()
2612 	adev->mode_info.crtcs[index] = amdgpu_crtc;  in dce_v8_0_crtc_init()
2614 	amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;  in dce_v8_0_crtc_init()
2615 	amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;  in dce_v8_0_crtc_init()
2616 	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;  in dce_v8_0_crtc_init()
2617 	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;  in dce_v8_0_crtc_init()
2619 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];  in dce_v8_0_crtc_init()
2621 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;  in dce_v8_0_crtc_init()
2622 	amdgpu_crtc->adjusted_clock = 0;  in dce_v8_0_crtc_init()
2623 	amdgpu_crtc->encoder = NULL;  in dce_v8_0_crtc_init()
2624 	amdgpu_crtc->connector = NULL;  in dce_v8_0_crtc_init()
2625 	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);  in dce_v8_0_crtc_init()
3118 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v8_0_pageflip_irq()  local
3122 	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v8_0_pageflip_irq()
3135 	if (amdgpu_crtc == NULL)  in dce_v8_0_pageflip_irq()
3139 	works = amdgpu_crtc->pflip_works;  in dce_v8_0_pageflip_irq()
3140 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){  in dce_v8_0_pageflip_irq()
3143 						amdgpu_crtc->pflip_status,  in dce_v8_0_pageflip_irq()
3150 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;  in dce_v8_0_pageflip_irq()
3151 	amdgpu_crtc->pflip_works = NULL;  in dce_v8_0_pageflip_irq()
3155 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);  in dce_v8_0_pageflip_irq()
3159 	drm_crtc_vblank_put(&amdgpu_crtc->base);  in dce_v8_0_pageflip_irq()