Lines Matching refs:amdgpu_crtc
194 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip() local
195 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v6_0_page_flip()
198 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v6_0_page_flip()
201 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
204 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
206 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
210 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v6_0_page_flip()
408 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_program_fmt() local
455 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_fmt()
826 struct amdgpu_crtc *amdgpu_crtc, in dce_v6_0_program_watermarks() argument
829 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v6_0_program_watermarks()
841 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
870 wm_high.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
872 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
897 wm_low.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
899 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
935 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
947 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
958 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
962 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
963 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
967 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
970 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
971 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
975 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); in dce_v6_0_program_watermarks()
978 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); in dce_v6_0_program_watermarks()
979 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); in dce_v6_0_program_watermarks()
982 amdgpu_crtc->line_time = line_time; in dce_v6_0_program_watermarks()
983 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v6_0_program_watermarks()
986 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v6_0_program_watermarks()
991 struct amdgpu_crtc *amdgpu_crtc, in dce_v6_0_line_buffer_adjust() argument
996 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust()
1010 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1023 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, in dce_v6_0_line_buffer_adjust()
1035 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1492 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_audio_set_dto() local
1504 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); in dce_v6_0_audio_set_dto()
1682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_afmt_setmode() local
1683 bpc = amdgpu_crtc->bpc; in dce_v6_0_afmt_setmode()
1789 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_vga_enable() local
1794 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v6_0_vga_enable()
1795 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); in dce_v6_0_vga_enable()
1800 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_grph_enable() local
1804 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); in dce_v6_0_grph_enable()
1811 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_do_set_base() local
1963 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1965 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1967 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1969 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1971 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1973 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
1974 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v6_0_crtc_do_set_base()
1981 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1988 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1989 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1990 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1991 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1992 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v6_0_crtc_do_set_base()
1993 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v6_0_crtc_do_set_base()
1996 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v6_0_crtc_do_set_base()
2000 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2004 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2009 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2013 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2036 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_set_interleave() local
2039 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, in dce_v6_0_set_interleave()
2042 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_set_interleave()
2048 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_load_lut() local
2054 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v6_0_crtc_load_lut()
2056 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2059 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2061 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2063 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2067 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2069 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2070 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2071 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2073 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2074 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2075 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2077 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2078 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v6_0_crtc_load_lut()
2080 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2085 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2091 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2096 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2099 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2102 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2106 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2148 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_pick_pll() local
2154 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v6_0_pick_pll()
2180 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_lock_cursor() local
2183 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v6_0_lock_cursor()
2188 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v6_0_lock_cursor()
2193 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_hide_cursor() local
2196 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_hide_cursor()
2205 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_show_cursor() local
2208 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2209 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2210 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2211 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2213 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2223 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_cursor_move_locked() local
2227 int w = amdgpu_crtc->cursor_width; in dce_v6_0_cursor_move_locked()
2229 amdgpu_crtc->cursor_x = x; in dce_v6_0_cursor_move_locked()
2230 amdgpu_crtc->cursor_y = y; in dce_v6_0_cursor_move_locked()
2238 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v6_0_cursor_move_locked()
2242 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v6_0_cursor_move_locked()
2246 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v6_0_cursor_move_locked()
2247 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v6_0_cursor_move_locked()
2248 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_cursor_move_locked()
2249 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v6_0_cursor_move_locked()
2274 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_cursor_set2() local
2286 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v6_0_crtc_cursor_set2()
2287 (height > amdgpu_crtc->max_cursor_height)) { in dce_v6_0_crtc_cursor_set2()
2294 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v6_0_crtc_cursor_set2()
2312 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v6_0_crtc_cursor_set2()
2316 if (width != amdgpu_crtc->cursor_width || in dce_v6_0_crtc_cursor_set2()
2317 height != amdgpu_crtc->cursor_height || in dce_v6_0_crtc_cursor_set2()
2318 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v6_0_crtc_cursor_set2()
2319 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v6_0_crtc_cursor_set2()
2322 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v6_0_crtc_cursor_set2()
2323 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v6_0_crtc_cursor_set2()
2327 amdgpu_crtc->cursor_width = width; in dce_v6_0_crtc_cursor_set2()
2328 amdgpu_crtc->cursor_height = height; in dce_v6_0_crtc_cursor_set2()
2329 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v6_0_crtc_cursor_set2()
2330 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v6_0_crtc_cursor_set2()
2337 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_crtc_cursor_set2()
2338 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2344 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2347 amdgpu_crtc->cursor_bo = obj; in dce_v6_0_crtc_cursor_set2()
2353 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_cursor_reset() local
2355 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_cursor_reset()
2358 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v6_0_cursor_reset()
2359 amdgpu_crtc->cursor_y); in dce_v6_0_cursor_reset()
2377 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_destroy() local
2380 kfree(amdgpu_crtc); in dce_v6_0_crtc_destroy()
2400 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_dpms() local
2405 amdgpu_crtc->enabled = true; in dce_v6_0_crtc_dpms()
2410 amdgpu_crtc->crtc_id); in dce_v6_0_crtc_dpms()
2420 if (amdgpu_crtc->enabled) in dce_v6_0_crtc_dpms()
2423 amdgpu_crtc->enabled = false; in dce_v6_0_crtc_dpms()
2447 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_disable() local
2475 i != amdgpu_crtc->crtc_id && in dce_v6_0_crtc_disable()
2476 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v6_0_crtc_disable()
2484 switch (amdgpu_crtc->pll_id) { in dce_v6_0_crtc_disable()
2488 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v6_0_crtc_disable()
2495 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_disable()
2496 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_disable()
2497 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_disable()
2498 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_disable()
2506 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_mode_set() local
2508 if (!amdgpu_crtc->adjusted_clock) in dce_v6_0_crtc_mode_set()
2518 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v6_0_crtc_mode_set()
2528 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_mode_fixup() local
2535 amdgpu_crtc->encoder = encoder; in dce_v6_0_crtc_mode_fixup()
2536 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v6_0_crtc_mode_fixup()
2540 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v6_0_crtc_mode_fixup()
2541 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_mode_fixup()
2542 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_mode_fixup()
2550 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); in dce_v6_0_crtc_mode_fixup()
2552 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v6_0_crtc_mode_fixup()
2553 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v6_0_crtc_mode_fixup()
2586 struct amdgpu_crtc *amdgpu_crtc; in dce_v6_0_crtc_init() local
2588 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + in dce_v6_0_crtc_init()
2590 if (amdgpu_crtc == NULL) in dce_v6_0_crtc_init()
2593 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); in dce_v6_0_crtc_init()
2595 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v6_0_crtc_init()
2596 amdgpu_crtc->crtc_id = index; in dce_v6_0_crtc_init()
2597 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v6_0_crtc_init()
2599 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; in dce_v6_0_crtc_init()
2600 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; in dce_v6_0_crtc_init()
2601 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v6_0_crtc_init()
2602 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v6_0_crtc_init()
2604 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()
2606 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_init()
2607 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_init()
2608 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_init()
2609 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_init()
2610 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); in dce_v6_0_crtc_init()
3025 struct amdgpu_crtc *amdgpu_crtc; in dce_v6_0_pageflip_irq() local
3029 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_pageflip_irq()
3042 if (amdgpu_crtc == NULL) in dce_v6_0_pageflip_irq()
3046 works = amdgpu_crtc->pflip_works; in dce_v6_0_pageflip_irq()
3047 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v6_0_pageflip_irq()
3050 amdgpu_crtc->pflip_status, in dce_v6_0_pageflip_irq()
3057 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v6_0_pageflip_irq()
3058 amdgpu_crtc->pflip_works = NULL; in dce_v6_0_pageflip_irq()
3062 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v6_0_pageflip_irq()
3066 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v6_0_pageflip_irq()