239 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v10_0_page_flip()  local
240 	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;  in dce_v10_0_page_flip()
244 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_page_flip()
247 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_page_flip()
249 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v10_0_page_flip()
252 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v10_0_page_flip()
255 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v10_0_page_flip()
258 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v10_0_page_flip()
510 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v10_0_program_fmt()  local
578 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_program_fmt()
596 				       struct amdgpu_crtc *amdgpu_crtc,  in dce_v10_0_line_buffer_adjust()  argument
600 	u32 pipe_offset = amdgpu_crtc->crtc_id;  in dce_v10_0_line_buffer_adjust()
609 	if (amdgpu_crtc->base.enabled && mode) {  in dce_v10_0_line_buffer_adjust()
629 	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);  in dce_v10_0_line_buffer_adjust()
631 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_line_buffer_adjust()
644 	if (amdgpu_crtc->base.enabled && mode) {  in dce_v10_0_line_buffer_adjust()
1028 					struct amdgpu_crtc *amdgpu_crtc,  in dce_v10_0_program_watermarks()  argument
1031 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;  in dce_v10_0_program_watermarks()
1038 	if (amdgpu_crtc->base.enabled && num_heads && mode) {  in dce_v10_0_program_watermarks()
1063 		wm_high.vsc = amdgpu_crtc->vsc;  in dce_v10_0_program_watermarks()
1065 		if (amdgpu_crtc->rmx_type != RMX_OFF)  in dce_v10_0_program_watermarks()
1102 		wm_low.vsc = amdgpu_crtc->vsc;  in dce_v10_0_program_watermarks()
1104 		if (amdgpu_crtc->rmx_type != RMX_OFF)  in dce_v10_0_program_watermarks()
1126 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_program_watermarks()
1128 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_program_watermarks()
1129 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_program_watermarks()
1132 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_program_watermarks()
1135 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_program_watermarks()
1136 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_program_watermarks()
1139 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_program_watermarks()
1141 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);  in dce_v10_0_program_watermarks()
1144 	amdgpu_crtc->line_time = line_time;  in dce_v10_0_program_watermarks()
1145 	amdgpu_crtc->wm_high = latency_watermark_a;  in dce_v10_0_program_watermarks()
1146 	amdgpu_crtc->wm_low = latency_watermark_b;  in dce_v10_0_program_watermarks()
1148 	amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;  in dce_v10_0_program_watermarks()
1545 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v10_0_audio_set_dto()  local
1560 			    amdgpu_crtc->crtc_id);  in dce_v10_0_audio_set_dto()
1592 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v10_0_afmt_setmode()  local
1593 		bpc = amdgpu_crtc->bpc;  in dce_v10_0_afmt_setmode()
1824 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_vga_enable()  local
1829 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;  in dce_v10_0_vga_enable()
1831 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);  in dce_v10_0_vga_enable()
1833 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);  in dce_v10_0_vga_enable()
1838 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_grph_enable()  local
1843 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);  in dce_v10_0_grph_enable()
1845 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_grph_enable()
1852 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_crtc_do_set_base()  local
2021 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_do_set_base()
2024 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_do_set_base()
2026 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v10_0_crtc_do_set_base()
2028 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v10_0_crtc_do_set_base()
2030 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v10_0_crtc_do_set_base()
2032 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v10_0_crtc_do_set_base()
2034 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v10_0_crtc_do_set_base()
2035 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v10_0_crtc_do_set_base()
2042 	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_do_set_base()
2047 	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_do_set_base()
2052 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_do_set_base()
2053 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_do_set_base()
2054 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_do_set_base()
2055 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_do_set_base()
2056 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v10_0_crtc_do_set_base()
2057 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v10_0_crtc_do_set_base()
2060 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v10_0_crtc_do_set_base()
2064 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v10_0_crtc_do_set_base()
2069 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v10_0_crtc_do_set_base()
2073 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v10_0_crtc_do_set_base()
2077 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_do_set_base()
2099 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_set_interleave()  local
2102 	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);  in dce_v10_0_set_interleave()
2107 	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_set_interleave()
2112 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_crtc_load_lut()  local
2119 	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);  in dce_v10_0_crtc_load_lut()
2121 	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2124 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2126 	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2128 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2130 	tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2132 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2134 	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2137 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2139 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_load_lut()
2141 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_load_lut()
2142 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_load_lut()
2143 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_load_lut()
2145 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v10_0_crtc_load_lut()
2146 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v10_0_crtc_load_lut()
2147 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v10_0_crtc_load_lut()
2149 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_load_lut()
2150 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v10_0_crtc_load_lut()
2152 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_load_lut()
2157 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v10_0_crtc_load_lut()
2163 	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2167 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2169 	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2172 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2174 	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2177 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2179 	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2182 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2185 	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v10_0_crtc_load_lut()
2189 	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_crtc_load_lut()
2191 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_crtc_load_lut()
2247 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_pick_pll()  local
2253 	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {  in dce_v10_0_pick_pll()
2285 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_lock_cursor()  local
2288 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v10_0_lock_cursor()
2293 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v10_0_lock_cursor()
2298 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_hide_cursor()  local
2302 	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_hide_cursor()
2304 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_hide_cursor()
2309 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_show_cursor()  local
2313 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v10_0_show_cursor()
2314 	       upper_32_bits(amdgpu_crtc->cursor_addr));  in dce_v10_0_show_cursor()
2315 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v10_0_show_cursor()
2316 	       lower_32_bits(amdgpu_crtc->cursor_addr));  in dce_v10_0_show_cursor()
2318 	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v10_0_show_cursor()
2321 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v10_0_show_cursor()
2327 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_cursor_move_locked()  local
2331 	amdgpu_crtc->cursor_x = x;  in dce_v10_0_cursor_move_locked()
2332 	amdgpu_crtc->cursor_y = y;  in dce_v10_0_cursor_move_locked()
2340 		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);  in dce_v10_0_cursor_move_locked()
2344 		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);  in dce_v10_0_cursor_move_locked()
2348 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v10_0_cursor_move_locked()
2349 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v10_0_cursor_move_locked()
2350 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v10_0_cursor_move_locked()
2351 	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));  in dce_v10_0_cursor_move_locked()
2376 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_crtc_cursor_set2()  local
2388 	if ((width > amdgpu_crtc->max_cursor_width) ||  in dce_v10_0_crtc_cursor_set2()
2389 	    (height > amdgpu_crtc->max_cursor_height)) {  in dce_v10_0_crtc_cursor_set2()
2396 		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);  in dce_v10_0_crtc_cursor_set2()
2414 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);  in dce_v10_0_crtc_cursor_set2()
2418 	if (width != amdgpu_crtc->cursor_width ||  in dce_v10_0_crtc_cursor_set2()
2419 	    height != amdgpu_crtc->cursor_height ||  in dce_v10_0_crtc_cursor_set2()
2420 	    hot_x != amdgpu_crtc->cursor_hot_x ||  in dce_v10_0_crtc_cursor_set2()
2421 	    hot_y != amdgpu_crtc->cursor_hot_y) {  in dce_v10_0_crtc_cursor_set2()
2424 		x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;  in dce_v10_0_crtc_cursor_set2()
2425 		y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;  in dce_v10_0_crtc_cursor_set2()
2429 		amdgpu_crtc->cursor_width = width;  in dce_v10_0_crtc_cursor_set2()
2430 		amdgpu_crtc->cursor_height = height;  in dce_v10_0_crtc_cursor_set2()
2431 		amdgpu_crtc->cursor_hot_x = hot_x;  in dce_v10_0_crtc_cursor_set2()
2432 		amdgpu_crtc->cursor_hot_y = hot_y;  in dce_v10_0_crtc_cursor_set2()
2439 	if (amdgpu_crtc->cursor_bo) {  in dce_v10_0_crtc_cursor_set2()
2440 		struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);  in dce_v10_0_crtc_cursor_set2()
2446 		drm_gem_object_put(amdgpu_crtc->cursor_bo);  in dce_v10_0_crtc_cursor_set2()
2449 	amdgpu_crtc->cursor_bo = obj;  in dce_v10_0_crtc_cursor_set2()
2455 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_cursor_reset()  local
2457 	if (amdgpu_crtc->cursor_bo) {  in dce_v10_0_cursor_reset()
2460 		dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,  in dce_v10_0_cursor_reset()
2461 					     amdgpu_crtc->cursor_y);  in dce_v10_0_cursor_reset()
2480 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_crtc_destroy()  local
2483 	kfree(amdgpu_crtc);  in dce_v10_0_crtc_destroy()
2503 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_crtc_dpms()  local
2508 		amdgpu_crtc->enabled = true;  in dce_v10_0_crtc_dpms()
2515 						amdgpu_crtc->crtc_id);  in dce_v10_0_crtc_dpms()
2525 		if (amdgpu_crtc->enabled) {  in dce_v10_0_crtc_dpms()
2531 		amdgpu_crtc->enabled = false;  in dce_v10_0_crtc_dpms()
2554 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_crtc_disable()  local
2582 		    i != amdgpu_crtc->crtc_id &&  in dce_v10_0_crtc_disable()
2583 		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {  in dce_v10_0_crtc_disable()
2591 	switch (amdgpu_crtc->pll_id) {  in dce_v10_0_crtc_disable()
2596 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,  in dce_v10_0_crtc_disable()
2603 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;  in dce_v10_0_crtc_disable()
2604 	amdgpu_crtc->adjusted_clock = 0;  in dce_v10_0_crtc_disable()
2605 	amdgpu_crtc->encoder = NULL;  in dce_v10_0_crtc_disable()
2606 	amdgpu_crtc->connector = NULL;  in dce_v10_0_crtc_disable()
2614 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_crtc_mode_set()  local
2616 	if (!amdgpu_crtc->adjusted_clock)  in dce_v10_0_crtc_mode_set()
2626 	amdgpu_crtc->hw_mode = *adjusted_mode;  in dce_v10_0_crtc_mode_set()
2635 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v10_0_crtc_mode_fixup()  local
2642 			amdgpu_crtc->encoder = encoder;  in dce_v10_0_crtc_mode_fixup()
2643 			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);  in dce_v10_0_crtc_mode_fixup()
2647 	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {  in dce_v10_0_crtc_mode_fixup()
2648 		amdgpu_crtc->encoder = NULL;  in dce_v10_0_crtc_mode_fixup()
2649 		amdgpu_crtc->connector = NULL;  in dce_v10_0_crtc_mode_fixup()
2657 	amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);  in dce_v10_0_crtc_mode_fixup()
2659 	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&  in dce_v10_0_crtc_mode_fixup()
2660 	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))  in dce_v10_0_crtc_mode_fixup()
2693 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v10_0_crtc_init()  local
2695 	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +  in dce_v10_0_crtc_init()
2697 	if (amdgpu_crtc == NULL)  in dce_v10_0_crtc_init()
2700 	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);  in dce_v10_0_crtc_init()
2702 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);  in dce_v10_0_crtc_init()
2703 	amdgpu_crtc->crtc_id = index;  in dce_v10_0_crtc_init()
2704 	adev->mode_info.crtcs[index] = amdgpu_crtc;  in dce_v10_0_crtc_init()
2706 	amdgpu_crtc->max_cursor_width = 128;  in dce_v10_0_crtc_init()
2707 	amdgpu_crtc->max_cursor_height = 128;  in dce_v10_0_crtc_init()
2708 	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;  in dce_v10_0_crtc_init()
2709 	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;  in dce_v10_0_crtc_init()
2711 	switch (amdgpu_crtc->crtc_id) {  in dce_v10_0_crtc_init()
2714 		amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;  in dce_v10_0_crtc_init()
2717 		amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;  in dce_v10_0_crtc_init()
2720 		amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;  in dce_v10_0_crtc_init()
2723 		amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;  in dce_v10_0_crtc_init()
2726 		amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;  in dce_v10_0_crtc_init()
2729 		amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;  in dce_v10_0_crtc_init()
2733 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;  in dce_v10_0_crtc_init()
2734 	amdgpu_crtc->adjusted_clock = 0;  in dce_v10_0_crtc_init()
2735 	amdgpu_crtc->encoder = NULL;  in dce_v10_0_crtc_init()
2736 	amdgpu_crtc->connector = NULL;  in dce_v10_0_crtc_init()
2737 	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);  in dce_v10_0_crtc_init()
3145 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v10_0_pageflip_irq()  local
3149 	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v10_0_pageflip_irq()
3162 	if (amdgpu_crtc == NULL)  in dce_v10_0_pageflip_irq()
3166 	works = amdgpu_crtc->pflip_works;  in dce_v10_0_pageflip_irq()
3167 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {  in dce_v10_0_pageflip_irq()
3170 						 amdgpu_crtc->pflip_status,  in dce_v10_0_pageflip_irq()
3177 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;  in dce_v10_0_pageflip_irq()
3178 	amdgpu_crtc->pflip_works = NULL;  in dce_v10_0_pageflip_irq()
3182 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);  in dce_v10_0_pageflip_irq()
3186 	drm_crtc_vblank_put(&amdgpu_crtc->base);  in dce_v10_0_pageflip_irq()