1218 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_afmt_audio_select_pin()
1221 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_audio_select_pin()
1222 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);  in dce_v10_0_afmt_audio_select_pin()
1223 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_audio_select_pin()
1239 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_latency_fields()
1269 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_latency_fields()
1286 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_speaker_allocation()
1310 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_speaker_allocation()
1323 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_speaker_allocation()
1356 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_sad_regs()
1409 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);  in dce_v10_0_audio_write_sad_regs()
1493 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1495 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1496 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1498 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1500 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1502 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1503 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1505 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1507 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1509 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1510 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1512 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1529 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1531 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1533 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1535 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1550 	if (!dig || !dig->afmt)  in dce_v10_0_audio_set_dto()
1583 	if (!dig || !dig->afmt)  in dce_v10_0_afmt_setmode()
1587 	if (!dig->afmt->enabled)  in dce_v10_0_afmt_setmode()
1597 	dig->afmt->pin = dce_v10_0_audio_get_pin(adev);  in dce_v10_0_afmt_setmode()
1598 	dce_v10_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v10_0_afmt_setmode()
1602 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1604 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */  in dce_v10_0_afmt_setmode()
1606 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);  in dce_v10_0_afmt_setmode()
1608 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1633 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1635 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1639 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1641 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1646 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1648 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1651 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1653 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1656 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1658 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */  in dce_v10_0_afmt_setmode()
1660 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1665 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1667 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1670 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1672 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1681 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1685 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1687 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1689 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1691 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1693 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1700 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1704 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,  in dce_v10_0_afmt_setmode()
1725 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1730 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1732 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1734 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1736 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1739 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1741 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);  in dce_v10_0_afmt_setmode()
1742 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);  in dce_v10_0_afmt_setmode()
1743 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);  in dce_v10_0_afmt_setmode()
1744 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);  in dce_v10_0_afmt_setmode()
1747 	dce_v10_0_audio_enable(adev, dig->afmt->pin, true);  in dce_v10_0_afmt_setmode()
1757 	if (!dig || !dig->afmt)  in dce_v10_0_afmt_enable()
1761 	if (enable && dig->afmt->enabled)  in dce_v10_0_afmt_enable()
1763 	if (!enable && !dig->afmt->enabled)  in dce_v10_0_afmt_enable()
1766 	if (!enable && dig->afmt->pin) {  in dce_v10_0_afmt_enable()
1767 		dce_v10_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v10_0_afmt_enable()
1768 		dig->afmt->pin = NULL;  in dce_v10_0_afmt_enable()
1771 	dig->afmt->enabled = enable;  in dce_v10_0_afmt_enable()
1774 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);  in dce_v10_0_afmt_enable()
1782 		adev->mode_info.afmt[i] = NULL;  in dce_v10_0_afmt_init()
1786 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);  in dce_v10_0_afmt_init()
1787 		if (adev->mode_info.afmt[i]) {  in dce_v10_0_afmt_init()
1788 			adev->mode_info.afmt[i]->offset = dig_offsets[i];  in dce_v10_0_afmt_init()
1789 			adev->mode_info.afmt[i]->id = i;  in dce_v10_0_afmt_init()
1793 				kfree(adev->mode_info.afmt[j]);  in dce_v10_0_afmt_init()
1794 				adev->mode_info.afmt[j] = NULL;  in dce_v10_0_afmt_init()
1807 		kfree(adev->mode_info.afmt[i]);  in dce_v10_0_afmt_fini()
1808 		adev->mode_info.afmt[i] = NULL;  in dce_v10_0_afmt_fini()
3365 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];  in dce_v10_0_encoder_prepare()