45 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)  in amdgpu_virt_mmio_blocked()  argument
53 void amdgpu_virt_init_setting(struct amdgpu_device *adev)  in amdgpu_virt_init_setting()  argument
55 	struct drm_device *ddev = adev_to_drm(adev);  in amdgpu_virt_init_setting()
58 	if (adev->asic_type != CHIP_ALDEBARAN &&  in amdgpu_virt_init_setting()
59 	    adev->asic_type != CHIP_ARCTURUS) {  in amdgpu_virt_init_setting()
60 		if (adev->mode_info.num_crtc == 0)  in amdgpu_virt_init_setting()
61 			adev->mode_info.num_crtc = 1;  in amdgpu_virt_init_setting()
62 		adev->enable_virtual_display = true;  in amdgpu_virt_init_setting()
65 	adev->cg_flags = 0;  in amdgpu_virt_init_setting()
66 	adev->pg_flags = 0;  in amdgpu_virt_init_setting()
69 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,  in amdgpu_virt_kiq_reg_write_reg_wait()  argument
73 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;  in amdgpu_virt_kiq_reg_write_reg_wait()
79 	if (adev->mes.ring.sched.ready) {  in amdgpu_virt_kiq_reg_write_reg_wait()
80 		amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,  in amdgpu_virt_kiq_reg_write_reg_wait()
118 	dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);  in amdgpu_virt_kiq_reg_write_reg_wait()
128 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)  in amdgpu_virt_request_full_gpu()  argument
130 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_request_full_gpu()
134 		r = virt->ops->req_full_gpu(adev, init);  in amdgpu_virt_request_full_gpu()
138 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_request_full_gpu()
151 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)  in amdgpu_virt_release_full_gpu()  argument
153 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_release_full_gpu()
157 		r = virt->ops->rel_full_gpu(adev, init);  in amdgpu_virt_release_full_gpu()
161 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_release_full_gpu()
172 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)  in amdgpu_virt_reset_gpu()  argument
174 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_reset_gpu()
178 		r = virt->ops->reset_gpu(adev);  in amdgpu_virt_reset_gpu()
182 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_reset_gpu()
188 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)  in amdgpu_virt_request_init_data()  argument
190 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_request_init_data()
193 		virt->ops->req_init_data(adev);  in amdgpu_virt_request_init_data()
195 	if (adev->virt.req_init_data_ver > 0)  in amdgpu_virt_request_init_data()
207 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)  in amdgpu_virt_wait_reset()  argument
209 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_wait_reset()
214 	return virt->ops->wait_reset(adev);  in amdgpu_virt_wait_reset()
223 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)  in amdgpu_virt_alloc_mm_table()  argument
227 	if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)  in amdgpu_virt_alloc_mm_table()
230 	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,  in amdgpu_virt_alloc_mm_table()
232 				    &adev->virt.mm_table.bo,  in amdgpu_virt_alloc_mm_table()
233 				    &adev->virt.mm_table.gpu_addr,  in amdgpu_virt_alloc_mm_table()
234 				    (void *)&adev->virt.mm_table.cpu_addr);  in amdgpu_virt_alloc_mm_table()
240 	memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);  in amdgpu_virt_alloc_mm_table()
242 		 adev->virt.mm_table.gpu_addr,  in amdgpu_virt_alloc_mm_table()
243 		 adev->virt.mm_table.cpu_addr);  in amdgpu_virt_alloc_mm_table()
252 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)  in amdgpu_virt_free_mm_table()  argument
254 	if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)  in amdgpu_virt_free_mm_table()
257 	amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,  in amdgpu_virt_free_mm_table()
258 			      &adev->virt.mm_table.gpu_addr,  in amdgpu_virt_free_mm_table()
259 			      (void *)&adev->virt.mm_table.cpu_addr);  in amdgpu_virt_free_mm_table()
260 	adev->virt.mm_table.gpu_addr = 0;  in amdgpu_virt_free_mm_table()
284 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)  in amdgpu_virt_init_ras_err_handler_data()  argument
286 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_init_ras_err_handler_data()
324 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)  in amdgpu_virt_ras_release_bp()  argument
326 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_release_bp()
342 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)  in amdgpu_virt_release_ras_err_handler_data()  argument
344 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_release_ras_err_handler_data()
352 	amdgpu_virt_ras_release_bp(adev);  in amdgpu_virt_release_ras_err_handler_data()
360 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,  in amdgpu_virt_ras_add_bps()  argument
363 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_add_bps()
373 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)  in amdgpu_virt_ras_reserve_bps()  argument
375 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_reserve_bps()
392 		if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,  in amdgpu_virt_ras_reserve_bps()
404 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,  in amdgpu_virt_ras_check_bad_page()  argument
407 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_check_bad_page()
421 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,  in amdgpu_virt_add_bad_page()  argument
431 			retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va +  in amdgpu_virt_add_bad_page()
435 			if (amdgpu_virt_ras_check_bad_page(adev, retired_page))  in amdgpu_virt_add_bad_page()
438 			amdgpu_virt_ras_add_bps(adev, &bp, 1);  in amdgpu_virt_add_bad_page()
440 			amdgpu_virt_ras_reserve_bps(adev);  in amdgpu_virt_add_bad_page()
445 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)  in amdgpu_virt_read_pf2vf_data()  argument
447 	struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;  in amdgpu_virt_read_pf2vf_data()
454 	if (adev->virt.fw_reserve.p_pf2vf == NULL)  in amdgpu_virt_read_pf2vf_data()
466 			adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,  in amdgpu_virt_read_pf2vf_data()
467 			adev->virt.fw_reserve.checksum_key, checksum);  in amdgpu_virt_read_pf2vf_data()
473 		adev->virt.gim_feature =  in amdgpu_virt_read_pf2vf_data()
480 			adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,  in amdgpu_virt_read_pf2vf_data()
487 		adev->virt.vf2pf_update_interval_ms =  in amdgpu_virt_read_pf2vf_data()
489 		adev->virt.gim_feature =  in amdgpu_virt_read_pf2vf_data()
491 		adev->virt.reg_access =  in amdgpu_virt_read_pf2vf_data()
494 		adev->virt.decode_max_dimension_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
495 		adev->virt.decode_max_frame_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
496 		adev->virt.encode_max_dimension_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
497 		adev->virt.encode_max_frame_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
498 		adev->virt.is_mm_bw_enabled = false;  in amdgpu_virt_read_pf2vf_data()
501 			adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);  in amdgpu_virt_read_pf2vf_data()
504 			adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);  in amdgpu_virt_read_pf2vf_data()
507 			adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);  in amdgpu_virt_read_pf2vf_data()
510 			adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);  in amdgpu_virt_read_pf2vf_data()
512 		if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))  in amdgpu_virt_read_pf2vf_data()
513 			adev->virt.is_mm_bw_enabled = true;  in amdgpu_virt_read_pf2vf_data()
515 		adev->unique_id =  in amdgpu_virt_read_pf2vf_data()
524 	if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)  in amdgpu_virt_read_pf2vf_data()
525 		adev->virt.vf2pf_update_interval_ms = 2000;  in amdgpu_virt_read_pf2vf_data()
530 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)  in amdgpu_virt_populate_vf2pf_ucode_info()  argument
533 	vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;  in amdgpu_virt_populate_vf2pf_ucode_info()
535 	if (adev->virt.fw_reserve.p_vf2pf == NULL)  in amdgpu_virt_populate_vf2pf_ucode_info()
538 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE,      adev->vce.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
539 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD,      adev->uvd.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
540 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC,       adev->gmc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
541 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME,       adev->gfx.me_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
542 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP,      adev->gfx.pfp_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
543 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE,       adev->gfx.ce_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
544 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC,      adev->gfx.rlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
545 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
546 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
547 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
548 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC,      adev->gfx.mec_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
549 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2,     adev->gfx.mec2_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
550 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_IMU,      adev->gfx.imu_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
551 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS,      adev->psp.sos.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
553 			    adev->psp.asd_context.bin_desc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
555 			    adev->psp.ras_context.context.bin_desc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
557 			    adev->psp.xgmi_context.context.bin_desc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
558 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC,      adev->pm.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
559 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA,     adev->sdma.instance[0].fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
560 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2,    adev->sdma.instance[1].fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
561 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN,      adev->vcn.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
562 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU,     adev->dm.dmcu_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
565 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)  in amdgpu_virt_write_vf2pf_data()  argument
569 	vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;  in amdgpu_virt_write_vf2pf_data()
571 	if (adev->virt.fw_reserve.p_vf2pf == NULL)  in amdgpu_virt_write_vf2pf_data()
591 		ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20;  in amdgpu_virt_write_vf2pf_data()
593 		amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20;  in amdgpu_virt_write_vf2pf_data()
594 	vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;  in amdgpu_virt_write_vf2pf_data()
595 	vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;  in amdgpu_virt_write_vf2pf_data()
597 	amdgpu_virt_populate_vf2pf_ucode_info(adev);  in amdgpu_virt_write_vf2pf_data()
605 	vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr;  in amdgpu_virt_write_vf2pf_data()
615 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);  in amdgpu_virt_update_vf2pf_work_item()  local
618 	ret = amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_update_vf2pf_work_item()
621 	amdgpu_virt_write_vf2pf_data(adev);  in amdgpu_virt_update_vf2pf_work_item()
624 	schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);  in amdgpu_virt_update_vf2pf_work_item()
627 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)  in amdgpu_virt_fini_data_exchange()  argument
629 	if (adev->virt.vf2pf_update_interval_ms != 0) {  in amdgpu_virt_fini_data_exchange()
631 		cancel_delayed_work_sync(&adev->virt.vf2pf_work);  in amdgpu_virt_fini_data_exchange()
632 		adev->virt.vf2pf_update_interval_ms = 0;  in amdgpu_virt_fini_data_exchange()
636 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)  in amdgpu_virt_init_data_exchange()  argument
638 	adev->virt.fw_reserve.p_pf2vf = NULL;  in amdgpu_virt_init_data_exchange()
639 	adev->virt.fw_reserve.p_vf2pf = NULL;  in amdgpu_virt_init_data_exchange()
640 	adev->virt.vf2pf_update_interval_ms = 0;  in amdgpu_virt_init_data_exchange()
642 	if (adev->mman.fw_vram_usage_va != NULL) {  in amdgpu_virt_init_data_exchange()
644 		amdgpu_virt_exchange_data(adev);  in amdgpu_virt_init_data_exchange()
646 		INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);  in amdgpu_virt_init_data_exchange()
647 …schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_…  in amdgpu_virt_init_data_exchange()
648 	} else if (adev->bios != NULL) {  in amdgpu_virt_init_data_exchange()
650 		adev->virt.fw_reserve.p_pf2vf =  in amdgpu_virt_init_data_exchange()
652 			(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));  in amdgpu_virt_init_data_exchange()
654 		amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_init_data_exchange()
659 void amdgpu_virt_exchange_data(struct amdgpu_device *adev)  in amdgpu_virt_exchange_data()  argument
665 	if (adev->mman.fw_vram_usage_va != NULL) {  in amdgpu_virt_exchange_data()
667 		adev->virt.fw_reserve.p_pf2vf =  in amdgpu_virt_exchange_data()
669 			(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));  in amdgpu_virt_exchange_data()
670 		adev->virt.fw_reserve.p_vf2pf =  in amdgpu_virt_exchange_data()
672 			(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));  in amdgpu_virt_exchange_data()
674 		amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_exchange_data()
675 		amdgpu_virt_write_vf2pf_data(adev);  in amdgpu_virt_exchange_data()
678 		if (adev->virt.fw_reserve.p_pf2vf->version == 2) {  in amdgpu_virt_exchange_data()
679 				pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;  in amdgpu_virt_exchange_data()
685 				if (bp_block_size && !adev->virt.ras_init_done)  in amdgpu_virt_exchange_data()
686 					amdgpu_virt_init_ras_err_handler_data(adev);  in amdgpu_virt_exchange_data()
688 				if (adev->virt.ras_init_done)  in amdgpu_virt_exchange_data()
689 					amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);  in amdgpu_virt_exchange_data()
694 void amdgpu_detect_virtualization(struct amdgpu_device *adev)  in amdgpu_detect_virtualization()  argument
698 	switch (adev->asic_type) {  in amdgpu_detect_virtualization()
719 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;  in amdgpu_detect_virtualization()
722 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;  in amdgpu_detect_virtualization()
727 			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;  in amdgpu_detect_virtualization()
730 	if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)  in amdgpu_detect_virtualization()
734 		adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;  in amdgpu_detect_virtualization()
737 	if (amdgpu_sriov_vf(adev)) {  in amdgpu_detect_virtualization()
738 		switch (adev->asic_type) {  in amdgpu_detect_virtualization()
741 			vi_set_virt_ops(adev);  in amdgpu_detect_virtualization()
744 			soc15_set_virt_ops(adev);  in amdgpu_detect_virtualization()
750 				amdgpu_virt_request_init_data(adev);  in amdgpu_detect_virtualization()
755 			soc15_set_virt_ops(adev);  in amdgpu_detect_virtualization()
761 			nv_set_virt_ops(adev);  in amdgpu_detect_virtualization()
763 			amdgpu_virt_request_init_data(adev);  in amdgpu_detect_virtualization()
766 			DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);  in amdgpu_detect_virtualization()
772 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)  in amdgpu_virt_access_debugfs_is_mmio()  argument
774 	return amdgpu_sriov_is_debug(adev) ? true : false;  in amdgpu_virt_access_debugfs_is_mmio()
777 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)  in amdgpu_virt_access_debugfs_is_kiq()  argument
779 	return amdgpu_sriov_is_normal(adev) ? true : false;  in amdgpu_virt_access_debugfs_is_kiq()
782 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)  in amdgpu_virt_enable_access_debugfs()  argument
784 	if (!amdgpu_sriov_vf(adev) ||  in amdgpu_virt_enable_access_debugfs()
785 	    amdgpu_virt_access_debugfs_is_kiq(adev))  in amdgpu_virt_enable_access_debugfs()
788 	if (amdgpu_virt_access_debugfs_is_mmio(adev))  in amdgpu_virt_enable_access_debugfs()
789 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_enable_access_debugfs()
796 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)  in amdgpu_virt_disable_access_debugfs()  argument
798 	if (amdgpu_sriov_vf(adev))  in amdgpu_virt_disable_access_debugfs()
799 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_disable_access_debugfs()
802 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)  in amdgpu_virt_get_sriov_vf_mode()  argument
806 	if (amdgpu_sriov_vf(adev)) {  in amdgpu_virt_get_sriov_vf_mode()
807 		if (amdgpu_sriov_is_pp_one_vf(adev))  in amdgpu_virt_get_sriov_vf_mode()
818 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)  in amdgpu_virt_fw_load_skip_check()  argument
820 	switch (adev->ip_versions[MP0_HWIP][0]) {  in amdgpu_virt_fw_load_skip_check()
872 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,  in amdgpu_virt_update_sriov_video_codec()  argument
878 	if (!adev->virt.is_mm_bw_enabled)  in amdgpu_virt_update_sriov_video_codec()
883 			encode[i].max_width = adev->virt.encode_max_dimension_pixels;  in amdgpu_virt_update_sriov_video_codec()
884 			encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;  in amdgpu_virt_update_sriov_video_codec()
894 			decode[i].max_width = adev->virt.decode_max_dimension_pixels;  in amdgpu_virt_update_sriov_video_codec()
895 			decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;  in amdgpu_virt_update_sriov_video_codec()
904 static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,  in amdgpu_virt_get_rlcg_reg_access_flag()  argument
912 		if (amdgpu_sriov_reg_indirect_gc(adev)) {  in amdgpu_virt_get_rlcg_reg_access_flag()
925 		if (amdgpu_sriov_reg_indirect_mmhub(adev) &&  in amdgpu_virt_get_rlcg_reg_access_flag()
937 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)  in amdgpu_virt_rlcg_reg_rw()  argument
949 	if (!adev->gfx.rlc.rlcg_reg_access_supported) {  in amdgpu_virt_rlcg_reg_rw()
950 		dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
955 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;  in amdgpu_virt_rlcg_reg_rw()
956 	scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;  in amdgpu_virt_rlcg_reg_rw()
957 	scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;  in amdgpu_virt_rlcg_reg_rw()
958 	scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;  in amdgpu_virt_rlcg_reg_rw()
959 	scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;  in amdgpu_virt_rlcg_reg_rw()
961 		spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;  in amdgpu_virt_rlcg_reg_rw()
966 		writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));  in amdgpu_virt_rlcg_reg_rw()
970 		writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));  in amdgpu_virt_rlcg_reg_rw()
991 			if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {  in amdgpu_virt_rlcg_reg_rw()
993 					dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
996 					dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
999 					dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
1002 					dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
1006 				dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
1016 void amdgpu_sriov_wreg(struct amdgpu_device *adev,  in amdgpu_sriov_wreg()  argument
1022 	if (!amdgpu_sriov_runtime(adev) &&  in amdgpu_sriov_wreg()
1023 		amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {  in amdgpu_sriov_wreg()
1024 		amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag);  in amdgpu_sriov_wreg()
1034 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,  in amdgpu_sriov_rreg()  argument
1039 	if (!amdgpu_sriov_runtime(adev) &&  in amdgpu_sriov_rreg()
1040 		amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))  in amdgpu_sriov_rreg()
1041 		return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag);  in amdgpu_sriov_rreg()