52 	ih->rptr = 0;  in amdgpu_ih_ring_init()
161 	if (wptr != READ_ONCE(ih->rptr)) {  in amdgpu_ih_ring_write()
192 		    ih->rptr == amdgpu_ih_get_wptr(adev, ih), timeout);  in amdgpu_ih_wait_on_checkpoint_process_ts()
216 	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);  in amdgpu_ih_process()
221 	while (ih->rptr != wptr && --count) {  in amdgpu_ih_process()
223 		ih->rptr &= ih->ptr_mask;  in amdgpu_ih_process()
231 	if (wptr != ih->rptr)  in amdgpu_ih_process()
253 	u32 ring_index = ih->rptr >> 2;  in amdgpu_ih_decode_iv_helper()
280 	ih->rptr += 32;  in amdgpu_ih_decode_iv_helper()
283 uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,  in amdgpu_ih_decode_iv_ts_helper()  argument
290 	rptr += iv_size * offset;  in amdgpu_ih_decode_iv_ts_helper()
291 	ring_index = (rptr & ih->ptr_mask) >> 2;  in amdgpu_ih_decode_iv_ts_helper()