Lines Matching defs:amdgpu_gfx_config

136 struct amdgpu_gfx_config {  struct
137 	unsigned max_shader_engines;
138 	unsigned max_tile_pipes;
139 	unsigned max_cu_per_sh;
140 	unsigned max_sh_per_se;
141 	unsigned max_backends_per_se;
142 	unsigned max_texture_channel_caches;
143 	unsigned max_gprs;
144 	unsigned max_gs_threads;
145 	unsigned max_hw_contexts;
146 	unsigned sc_prim_fifo_size_frontend;
147 	unsigned sc_prim_fifo_size_backend;
148 	unsigned sc_hiz_tile_fifo_size;
149 	unsigned sc_earlyz_tile_fifo_size;
151 	unsigned num_tile_pipes;
152 	unsigned backend_enable_mask;
153 	unsigned mem_max_burst_length_bytes;
154 	unsigned mem_row_size_in_kb;
155 	unsigned shader_engine_tile_size;
156 	unsigned num_gpus;
157 	unsigned multi_gpu_tile_size;
158 	unsigned mc_arb_ramcfg;
159 	unsigned num_banks;
160 	unsigned num_ranks;
161 	unsigned gb_addr_config;
162 	unsigned num_rbs;
163 	unsigned gs_vgt_table_depth;
164 	unsigned gs_prim_buffer_depth;
166 	uint32_t tile_mode_array[32];
167 	uint32_t macrotile_mode_array[16];
169 	struct gb_addr_config gb_addr_config_fields;
170 	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
173 	uint32_t double_offchip_lds_buf;
175 	uint32_t db_debug2;
177 	uint32_t num_sc_per_sh;
178 	uint32_t num_packer_per_sc;
179 	uint32_t pa_sc_tile_steering_override;
180 	uint64_t tcc_disabled_mask;
181 	uint32_t gc_num_tcp_per_sa;
182 	uint32_t gc_num_sdp_interface;
183 	uint32_t gc_num_tcps;
184 	uint32_t gc_num_tcp_per_wpg;
185 	uint32_t gc_tcp_l1_size;
186 	uint32_t gc_num_sqc_per_wgp;
187 	uint32_t gc_l1_instruction_cache_size_per_sqc;
188 	uint32_t gc_l1_data_cache_size_per_sqc;
189 	uint32_t gc_gl1c_per_sa;
190 	uint32_t gc_gl1c_size_per_instance;
191 	uint32_t gc_gl2c_per_gpu;