128 	void __iomem *base_addr;  member
236 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
239 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
244 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
247 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
252 		data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
292 	writel_relaxed(state, gpio->base_addr + reg_offset);  in zynq_gpio_set_value()
324 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
326 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
356 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
358 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
361 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
363 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
388 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_get_direction()
413 		       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));  in zynq_gpio_irq_mask()
434 		       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));  in zynq_gpio_irq_unmask()
454 		       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));  in zynq_gpio_irq_ack()
505 	int_type = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
507 	int_pol = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
509 	int_any = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
544 		       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
546 		       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
548 		       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
656 		int_sts = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
658 		int_enb = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
674 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
677 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
679 		gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
681 		gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
684 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
687 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
690 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
702 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_restore_context()
705 			       gpio->base_addr +  in zynq_gpio_restore_context()
708 			       gpio->base_addr +  in zynq_gpio_restore_context()
711 			       gpio->base_addr +  in zynq_gpio_restore_context()
714 			       gpio->base_addr +  in zynq_gpio_restore_context()
717 			       gpio->base_addr +  in zynq_gpio_restore_context()
720 			       gpio->base_addr +  in zynq_gpio_restore_context()
723 			       gpio->base_addr +  in zynq_gpio_restore_context()
913 	gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);  in zynq_gpio_probe()
914 	if (IS_ERR(gpio->base_addr))  in zynq_gpio_probe()
915 		return PTR_ERR(gpio->base_addr);  in zynq_gpio_probe()
957 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_probe()