Lines Matching refs:g

77 	struct davinci_gpio_regs __iomem *g;  in irq2regs()  local
79 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); in irq2regs()
81 return g; in irq2regs()
93 struct davinci_gpio_regs __iomem *g; in __davinci_direction() local
99 g = d->regs[bank]; in __davinci_direction()
101 temp = readl_relaxed(&g->dir); in __davinci_direction()
104 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
108 writel_relaxed(temp, &g->dir); in __davinci_direction()
135 struct davinci_gpio_regs __iomem *g; in davinci_gpio_get() local
138 g = d->regs[bank]; in davinci_gpio_get()
140 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
150 struct davinci_gpio_regs __iomem *g; in davinci_gpio_set() local
153 g = d->regs[bank]; in davinci_gpio_set()
156 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
295 struct davinci_gpio_regs __iomem *g = irq2regs(d); in gpio_irq_disable() local
298 writel_relaxed(mask, &g->clr_falling); in gpio_irq_disable()
299 writel_relaxed(mask, &g->clr_rising); in gpio_irq_disable()
304 struct davinci_gpio_regs __iomem *g = irq2regs(d); in gpio_irq_enable() local
313 writel_relaxed(mask, &g->set_falling); in gpio_irq_enable()
315 writel_relaxed(mask, &g->set_rising); in gpio_irq_enable()
336 struct davinci_gpio_regs __iomem *g; in gpio_irq_handler() local
344 g = irqdata->regs; in gpio_irq_handler()
359 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
362 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
408 struct davinci_gpio_regs __iomem *g; in gpio_irq_type_unbanked() local
412 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
426 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
428 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
439 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; in davinci_gpio_irq_map() local
444 irq_set_chip_data(irq, (__force void *)g); in davinci_gpio_irq_map()
493 struct davinci_gpio_regs __iomem *g; in davinci_gpio_irq_setup() local
566 g = chips->regs[0]; in davinci_gpio_irq_setup()
567 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
568 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
590 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
591 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
592 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
608 irqdata->regs = g; in davinci_gpio_irq_setup()
631 struct davinci_gpio_regs __iomem *g; in davinci_gpio_save_context() local
640 g = chips->regs[bank]; in davinci_gpio_save_context()
642 context->dir = readl_relaxed(&g->dir); in davinci_gpio_save_context()
643 context->set_data = readl_relaxed(&g->set_data); in davinci_gpio_save_context()
644 context->set_rising = readl_relaxed(&g->set_rising); in davinci_gpio_save_context()
645 context->set_falling = readl_relaxed(&g->set_falling); in davinci_gpio_save_context()
652 writel_relaxed(GENMASK(31, 0), &g->intstat); in davinci_gpio_save_context()
658 struct davinci_gpio_regs __iomem *g; in davinci_gpio_restore_context() local
669 g = chips->regs[bank]; in davinci_gpio_restore_context()
671 if (readl_relaxed(&g->dir) != context->dir) in davinci_gpio_restore_context()
672 writel_relaxed(context->dir, &g->dir); in davinci_gpio_restore_context()
673 if (readl_relaxed(&g->set_data) != context->set_data) in davinci_gpio_restore_context()
674 writel_relaxed(context->set_data, &g->set_data); in davinci_gpio_restore_context()
675 if (readl_relaxed(&g->set_rising) != context->set_rising) in davinci_gpio_restore_context()
676 writel_relaxed(context->set_rising, &g->set_rising); in davinci_gpio_restore_context()
677 if (readl_relaxed(&g->set_falling) != context->set_falling) in davinci_gpio_restore_context()
678 writel_relaxed(context->set_falling, &g->set_falling); in davinci_gpio_restore_context()