208 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,  in bank_reg()  function
309 	void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);  in aspeed_gpio_change_cmd_source()
310 	void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);  in aspeed_gpio_change_cmd_source()
356 	gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));  in aspeed_gpio_copro_request()
386 	return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));  in aspeed_gpio_get()
397 	addr = bank_reg(gpio, bank, reg_val);  in __aspeed_gpio_set()
430 	void __iomem *addr = bank_reg(gpio, bank, reg_dir);  in aspeed_gpio_dir_in()
458 	void __iomem *addr = bank_reg(gpio, bank, reg_dir);  in aspeed_gpio_dir_out()
497 	val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);  in aspeed_gpio_get_direction()
540 	status_addr = bank_reg(gpio, bank, reg_irq_status);  in aspeed_gpio_irq_ack()
566 	addr = bank_reg(gpio, bank, reg_irq_enable);  in aspeed_gpio_irq_set_mask()
635 	addr = bank_reg(gpio, bank, reg_irq_type0);  in aspeed_gpio_set_type()
640 	addr = bank_reg(gpio, bank, reg_irq_type1);  in aspeed_gpio_set_type()
645 	addr = bank_reg(gpio, bank, reg_irq_type2);  in aspeed_gpio_set_type()
674 		reg = ioread32(bank_reg(data, bank, reg_irq_status));  in aspeed_gpio_irq_handler()
717 	treg = bank_reg(gpio, to_bank(offset), reg_tolerance);  in aspeed_gpio_reset_tolerance()
831 	addr = bank_reg(gpio, bank, reg_debounce_sel1);  in configure_timer()
835 	addr = bank_reg(gpio, bank, reg_debounce_sel2);  in configure_timer()
1195 		void __iomem *addr = bank_reg(gpio, bank, reg_rdata);  in aspeed_gpio_probe()