Lines Matching refs:bank_reg
103 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() function
179 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
198 addr_r = bank_reg(gpio, bank, reg_rdata); in sgpio_set_value()
199 addr_w = bank_reg(gpio, bank, reg_val); in sgpio_set_value()
278 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_sgpio_irq_ack()
297 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_sgpio_irq_set_mask()
360 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_sgpio_set_type()
365 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_sgpio_set_type()
370 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_sgpio_set_type()
395 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_sgpio_irq_handler()
421 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable)); in aspeed_sgpio_setup_irqs()
423 iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status)); in aspeed_sgpio_setup_irqs()
446 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0)); in aspeed_sgpio_setup_irqs()
448 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1)); in aspeed_sgpio_setup_irqs()
450 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2)); in aspeed_sgpio_setup_irqs()
468 reg = bank_reg(gpio, to_bank(offset), reg_tolerance); in aspeed_sgpio_reset_tolerance()