34 static const u32 ctrl_base = 0x80000000;  variable
228 		opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0);  in check_errors()
229 		opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0);  in check_errors()
230 		opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0);  in check_errors()
242 		ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0,  in check_errors()
340 		ret = opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx), reg);  in aspeed_master_link_enable()
344 	ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg);  in aspeed_master_link_enable()
401 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
406 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
409 	opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg);  in aspeed_master_init()
417 	opb_writel(aspeed, ctrl_base + FSI_MMODE, reg);  in aspeed_master_init()
420 	opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg);  in aspeed_master_init()
423 	opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg);  in aspeed_master_init()
428 	opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg);  in aspeed_master_init()
430 	opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL);  in aspeed_master_init()
433 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
435 	opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL);  in aspeed_master_init()
439 	opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);  in aspeed_master_init()
442 	opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);  in aspeed_master_init()
583 	writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);  in fsi_master_aspeed_probe()
600 	rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw);  in fsi_master_aspeed_probe()