Lines Matching refs:pvt
396 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) argument
397 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) argument
400 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) argument
401 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) argument
489 struct i7core_pvt *pvt = mci->pvt_info; in get_dimm_config() local
497 pdev = pvt->pci_mcr[0]; in get_dimm_config()
502 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); in get_dimm_config()
503 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); in get_dimm_config()
504 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); in get_dimm_config()
505 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); in get_dimm_config()
508 pvt->i7core_dev->socket, pvt->info.mc_control, in get_dimm_config()
509 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map); in get_dimm_config()
511 if (ECC_ENABLED(pvt)) { in get_dimm_config()
512 edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); in get_dimm_config()
513 if (ECCx8(pvt)) in get_dimm_config()
524 numdimms(pvt->info.max_dod), in get_dimm_config()
525 numrank(pvt->info.max_dod >> 2), in get_dimm_config()
526 numbank(pvt->info.max_dod >> 4), in get_dimm_config()
527 numrow(pvt->info.max_dod >> 6), in get_dimm_config()
528 numcol(pvt->info.max_dod >> 9)); in get_dimm_config()
533 if (!pvt->pci_ch[i][0]) in get_dimm_config()
536 if (!CH_ACTIVE(pvt, i)) { in get_dimm_config()
540 if (CH_DISABLED(pvt, i)) { in get_dimm_config()
546 pci_read_config_dword(pvt->pci_ch[i][0], in get_dimm_config()
551 pvt->channel[i].is_3dimms_present = true; in get_dimm_config()
554 pvt->channel[i].is_single_4rank = true; in get_dimm_config()
557 pvt->channel[i].has_4rank = true; in get_dimm_config()
565 pci_read_config_dword(pvt->pci_ch[i][1], in get_dimm_config()
567 pci_read_config_dword(pvt->pci_ch[i][1], in get_dimm_config()
569 pci_read_config_dword(pvt->pci_ch[i][1], in get_dimm_config()
574 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), in get_dimm_config()
576 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "", in get_dimm_config()
577 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "", in get_dimm_config()
578 pvt->channel[i].has_4rank ? "HAS_4R " : "", in get_dimm_config()
622 pvt->i7core_dev->socket, i, j); in get_dimm_config()
662 struct i7core_pvt *pvt = mci->pvt_info; in disable_inject() local
664 pvt->inject.enable = 0; in disable_inject()
666 if (!pvt->pci_ch[pvt->inject.channel][0]) in disable_inject()
669 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], in disable_inject()
687 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_section_store() local
691 if (pvt->inject.enable) in i7core_inject_section_store()
698 pvt->inject.section = (u32) value; in i7core_inject_section_store()
707 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_section_show() local
708 return sprintf(data, "0x%08x\n", pvt->inject.section); in i7core_inject_section_show()
724 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_type_store() local
728 if (pvt->inject.enable) in i7core_inject_type_store()
735 pvt->inject.type = (u32) value; in i7core_inject_type_store()
744 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_type_show() local
746 return sprintf(data, "0x%08x\n", pvt->inject.type); in i7core_inject_type_show()
764 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_eccmask_store() local
768 if (pvt->inject.enable) in i7core_inject_eccmask_store()
775 pvt->inject.eccmask = (u32) value; in i7core_inject_eccmask_store()
784 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_eccmask_show() local
786 return sprintf(data, "0x%08x\n", pvt->inject.eccmask); in i7core_inject_eccmask_show()
807 struct i7core_pvt *pvt; \
812 pvt = mci->pvt_info; \
814 if (pvt->inject.enable) \
825 pvt->inject.param = value; \
836 struct i7core_pvt *pvt; \
838 pvt = mci->pvt_info; \
839 edac_dbg(1, "pvt=%p\n", pvt); \
840 if (pvt->inject.param < 0) \
843 return sprintf(data, "%d\n", pvt->inject.param);\
915 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_enable_store() local
921 if (!pvt->pci_ch[pvt->inject.channel][0]) in i7core_inject_enable_store()
929 pvt->inject.enable = 1; in i7core_inject_enable_store()
936 if (pvt->inject.dimm < 0) in i7core_inject_enable_store()
939 if (pvt->channel[pvt->inject.channel].dimms > 2) in i7core_inject_enable_store()
940 mask |= (pvt->inject.dimm & 0x3LL) << 35; in i7core_inject_enable_store()
942 mask |= (pvt->inject.dimm & 0x1LL) << 36; in i7core_inject_enable_store()
946 if (pvt->inject.rank < 0) in i7core_inject_enable_store()
949 if (pvt->channel[pvt->inject.channel].dimms > 2) in i7core_inject_enable_store()
950 mask |= (pvt->inject.rank & 0x1LL) << 34; in i7core_inject_enable_store()
952 mask |= (pvt->inject.rank & 0x3LL) << 34; in i7core_inject_enable_store()
956 if (pvt->inject.bank < 0) in i7core_inject_enable_store()
959 mask |= (pvt->inject.bank & 0x15LL) << 30; in i7core_inject_enable_store()
962 if (pvt->inject.page < 0) in i7core_inject_enable_store()
965 mask |= (pvt->inject.page & 0xffff) << 14; in i7core_inject_enable_store()
968 if (pvt->inject.col < 0) in i7core_inject_enable_store()
971 mask |= (pvt->inject.col & 0x3fff); in i7core_inject_enable_store()
980 injectmask = (pvt->inject.type & 1) | in i7core_inject_enable_store()
981 (pvt->inject.section & 0x3) << 1 | in i7core_inject_enable_store()
982 (pvt->inject.type & 0x6) << (3 - 1); in i7core_inject_enable_store()
985 pci_write_config_dword(pvt->pci_noncore, in i7core_inject_enable_store()
988 write_and_test(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_store()
990 write_and_test(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_store()
993 write_and_test(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_store()
994 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); in i7core_inject_enable_store()
996 write_and_test(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_store()
1004 pci_write_config_dword(pvt->pci_noncore, in i7core_inject_enable_store()
1008 mask, pvt->inject.eccmask, injectmask); in i7core_inject_enable_store()
1019 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_enable_show() local
1022 if (!pvt->pci_ch[pvt->inject.channel][0]) in i7core_inject_enable_show()
1025 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_show()
1031 pvt->inject.enable = 1; in i7core_inject_enable_show()
1033 return sprintf(data, "%d\n", pvt->inject.enable); in i7core_inject_enable_show()
1043 struct i7core_pvt *pvt = mci->pvt_info; \
1046 if (!pvt->ce_count_available || (pvt->is_registered)) \
1049 pvt->udimm_ce_count[param]); \
1159 struct i7core_pvt *pvt = mci->pvt_info; in i7core_create_sysfs_devices() local
1162 pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL); in i7core_create_sysfs_devices()
1163 if (!pvt->addrmatch_dev) in i7core_create_sysfs_devices()
1166 pvt->addrmatch_dev->type = &addrmatch_type; in i7core_create_sysfs_devices()
1167 pvt->addrmatch_dev->bus = mci->dev.bus; in i7core_create_sysfs_devices()
1168 device_initialize(pvt->addrmatch_dev); in i7core_create_sysfs_devices()
1169 pvt->addrmatch_dev->parent = &mci->dev; in i7core_create_sysfs_devices()
1170 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch"); in i7core_create_sysfs_devices()
1171 dev_set_drvdata(pvt->addrmatch_dev, mci); in i7core_create_sysfs_devices()
1173 edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev)); in i7core_create_sysfs_devices()
1175 rc = device_add(pvt->addrmatch_dev); in i7core_create_sysfs_devices()
1179 if (!pvt->is_registered) { in i7core_create_sysfs_devices()
1180 pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev), in i7core_create_sysfs_devices()
1182 if (!pvt->chancounts_dev) { in i7core_create_sysfs_devices()
1187 pvt->chancounts_dev->type = &all_channel_counts_type; in i7core_create_sysfs_devices()
1188 pvt->chancounts_dev->bus = mci->dev.bus; in i7core_create_sysfs_devices()
1189 device_initialize(pvt->chancounts_dev); in i7core_create_sysfs_devices()
1190 pvt->chancounts_dev->parent = &mci->dev; in i7core_create_sysfs_devices()
1191 dev_set_name(pvt->chancounts_dev, "all_channel_counts"); in i7core_create_sysfs_devices()
1192 dev_set_drvdata(pvt->chancounts_dev, mci); in i7core_create_sysfs_devices()
1194 edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev)); in i7core_create_sysfs_devices()
1196 rc = device_add(pvt->chancounts_dev); in i7core_create_sysfs_devices()
1203 put_device(pvt->chancounts_dev); in i7core_create_sysfs_devices()
1205 device_del(pvt->addrmatch_dev); in i7core_create_sysfs_devices()
1207 put_device(pvt->addrmatch_dev); in i7core_create_sysfs_devices()
1214 struct i7core_pvt *pvt = mci->pvt_info; in i7core_delete_sysfs_devices() local
1218 if (!pvt->is_registered) { in i7core_delete_sysfs_devices()
1219 device_del(pvt->chancounts_dev); in i7core_delete_sysfs_devices()
1220 put_device(pvt->chancounts_dev); in i7core_delete_sysfs_devices()
1222 device_del(pvt->addrmatch_dev); in i7core_delete_sysfs_devices()
1223 put_device(pvt->addrmatch_dev); in i7core_delete_sysfs_devices()
1455 struct i7core_pvt *pvt = mci->pvt_info; in mci_bind_devs() local
1460 pvt->is_registered = false; in mci_bind_devs()
1461 pvt->enable_scrub = false; in mci_bind_devs()
1472 pvt->pci_mcr[func] = pdev; in mci_bind_devs()
1476 pvt->pci_ch[slot - 4][func] = pdev; in mci_bind_devs()
1478 pvt->pci_noncore = pdev; in mci_bind_devs()
1484 pvt->enable_scrub = false; in mci_bind_devs()
1488 pvt->enable_scrub = false; in mci_bind_devs()
1492 pvt->enable_scrub = false; in mci_bind_devs()
1496 pvt->enable_scrub = true; in mci_bind_devs()
1500 pvt->enable_scrub = true; in mci_bind_devs()
1504 pvt->enable_scrub = false; in mci_bind_devs()
1516 pvt->is_registered = true; in mci_bind_devs()
1538 struct i7core_pvt *pvt = mci->pvt_info; in i7core_rdimm_update_ce_count() local
1541 if (pvt->ce_count_available) { in i7core_rdimm_update_ce_count()
1544 add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; in i7core_rdimm_update_ce_count()
1545 add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; in i7core_rdimm_update_ce_count()
1546 add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; in i7core_rdimm_update_ce_count()
1550 pvt->rdimm_ce_count[chan][2] += add2; in i7core_rdimm_update_ce_count()
1554 pvt->rdimm_ce_count[chan][1] += add1; in i7core_rdimm_update_ce_count()
1558 pvt->rdimm_ce_count[chan][0] += add0; in i7core_rdimm_update_ce_count()
1560 pvt->ce_count_available = 1; in i7core_rdimm_update_ce_count()
1563 pvt->rdimm_last_ce_count[chan][2] = new2; in i7core_rdimm_update_ce_count()
1564 pvt->rdimm_last_ce_count[chan][1] = new1; in i7core_rdimm_update_ce_count()
1565 pvt->rdimm_last_ce_count[chan][0] = new0; in i7core_rdimm_update_ce_count()
1584 struct i7core_pvt *pvt = mci->pvt_info; in i7core_rdimm_check_mc_ecc_err() local
1589 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, in i7core_rdimm_check_mc_ecc_err()
1591 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, in i7core_rdimm_check_mc_ecc_err()
1593 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, in i7core_rdimm_check_mc_ecc_err()
1595 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, in i7core_rdimm_check_mc_ecc_err()
1597 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, in i7core_rdimm_check_mc_ecc_err()
1599 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, in i7core_rdimm_check_mc_ecc_err()
1605 if (pvt->channel[i].dimms > 2) { in i7core_rdimm_check_mc_ecc_err()
1629 struct i7core_pvt *pvt = mci->pvt_info; in i7core_udimm_check_mc_ecc_err() local
1633 if (!pvt->pci_mcr[4]) { in i7core_udimm_check_mc_ecc_err()
1639 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); in i7core_udimm_check_mc_ecc_err()
1640 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); in i7core_udimm_check_mc_ecc_err()
1648 if (pvt->ce_count_available) { in i7core_udimm_check_mc_ecc_err()
1652 add2 = new2 - pvt->udimm_last_ce_count[2]; in i7core_udimm_check_mc_ecc_err()
1653 add1 = new1 - pvt->udimm_last_ce_count[1]; in i7core_udimm_check_mc_ecc_err()
1654 add0 = new0 - pvt->udimm_last_ce_count[0]; in i7core_udimm_check_mc_ecc_err()
1658 pvt->udimm_ce_count[2] += add2; in i7core_udimm_check_mc_ecc_err()
1662 pvt->udimm_ce_count[1] += add1; in i7core_udimm_check_mc_ecc_err()
1666 pvt->udimm_ce_count[0] += add0; in i7core_udimm_check_mc_ecc_err()
1673 pvt->ce_count_available = 1; in i7core_udimm_check_mc_ecc_err()
1676 pvt->udimm_last_ce_count[2] = new2; in i7core_udimm_check_mc_ecc_err()
1677 pvt->udimm_last_ce_count[1] = new1; in i7core_udimm_check_mc_ecc_err()
1678 pvt->udimm_last_ce_count[0] = new0; in i7core_udimm_check_mc_ecc_err()
1697 struct i7core_pvt *pvt = mci->pvt_info; in i7core_mce_output_error() local
1778 if (uncorrected_error || !pvt->is_registered) in i7core_mce_output_error()
1793 struct i7core_pvt *pvt = mci->pvt_info; in i7core_check_error() local
1800 if (!pvt->is_registered) in i7core_check_error()
1959 struct i7core_pvt *pvt = mci->pvt_info; in set_sdram_scrub_rate() local
1965 pdev = pvt->pci_mcr[2]; in set_sdram_scrub_rate()
1984 const u32 freq_dclk_mhz = pvt->dclk_freq; in set_sdram_scrub_rate()
2021 struct i7core_pvt *pvt = mci->pvt_info; in get_sdram_scrub_rate() local
2024 const u32 freq_dclk_mhz = pvt->dclk_freq; in get_sdram_scrub_rate()
2029 pdev = pvt->pci_mcr[2]; in get_sdram_scrub_rate()
2050 struct i7core_pvt *pvt = mci->pvt_info; in enable_sdram_scrub_setting() local
2054 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); in enable_sdram_scrub_setting()
2056 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, in enable_sdram_scrub_setting()
2065 struct i7core_pvt *pvt = mci->pvt_info; in disable_sdram_scrub_setting() local
2069 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); in disable_sdram_scrub_setting()
2071 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, in disable_sdram_scrub_setting()
2075 static void i7core_pci_ctl_create(struct i7core_pvt *pvt) in i7core_pci_ctl_create() argument
2077 pvt->i7core_pci = edac_pci_create_generic_ctl( in i7core_pci_ctl_create()
2078 &pvt->i7core_dev->pdev[0]->dev, in i7core_pci_ctl_create()
2080 if (unlikely(!pvt->i7core_pci)) in i7core_pci_ctl_create()
2085 static void i7core_pci_ctl_release(struct i7core_pvt *pvt) in i7core_pci_ctl_release() argument
2087 if (likely(pvt->i7core_pci)) in i7core_pci_ctl_release()
2088 edac_pci_release_generic_ctl(pvt->i7core_pci); in i7core_pci_ctl_release()
2092 pvt->i7core_dev->socket); in i7core_pci_ctl_release()
2093 pvt->i7core_pci = NULL; in i7core_pci_ctl_release()
2099 struct i7core_pvt *pvt; in i7core_unregister_mci() local
2108 pvt = mci->pvt_info; in i7core_unregister_mci()
2113 if (pvt->enable_scrub) in i7core_unregister_mci()
2117 i7core_pci_ctl_release(pvt); in i7core_unregister_mci()
2132 struct i7core_pvt *pvt; in i7core_register_mci() local
2145 sizeof(*pvt)); in i7core_register_mci()
2151 pvt = mci->pvt_info; in i7core_register_mci()
2152 memset(pvt, 0, sizeof(*pvt)); in i7core_register_mci()
2155 pvt->i7core_dev = i7core_dev; in i7core_register_mci()
2189 if (pvt->enable_scrub) in i7core_register_mci()
2210 pvt->inject.channel = 0; in i7core_register_mci()
2211 pvt->inject.dimm = -1; in i7core_register_mci()
2212 pvt->inject.rank = -1; in i7core_register_mci()
2213 pvt->inject.bank = -1; in i7core_register_mci()
2214 pvt->inject.page = -1; in i7core_register_mci()
2215 pvt->inject.col = -1; in i7core_register_mci()
2218 i7core_pci_ctl_create(pvt); in i7core_register_mci()
2221 pvt->dclk_freq = get_dclk_freq(); in i7core_register_mci()