487 	edac_dbg(0, "\t\tCSROW= %d  Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",  in i5000_process_fatal_error_info()
566 		edac_dbg(0, "\tUncorrected bits= 0x%x\n", ue_errors);  in i5000_process_nonfatal_error_info()
582 …edac_dbg(0, "\t\tCSROW= %d  Channels= %d,%d  (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n…  in i5000_process_nonfatal_error_info()
636 		edac_dbg(0, "\tCorrected bits= 0x%x\n", ce_errors);  in i5000_process_nonfatal_error_info()
654 		edac_dbg(0, "\t\tCSROW= %d Channel= %d  (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",  in i5000_process_nonfatal_error_info()
839 	edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s  %x:%x\n",  in i5000_get_devices()
842 	edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",  in i5000_get_devices()
846 	edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s  %x:%x\n",  in i5000_get_devices()
971 	edac_dbg(2, "\tMTR%d=0x%x:  DIMMs are %sPresent\n",  in decode_mtr()
976 	edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));  in decode_mtr()
977 	edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));  in decode_mtr()
978 	edac_dbg(2, "\t\tNUMRANK: %s\n",  in decode_mtr()
980 	edac_dbg(2, "\t\tNUMROW: %s\n",  in decode_mtr()
985 	edac_dbg(2, "\t\tNUMCOL: %s\n",  in decode_mtr()
1064 			edac_dbg(2, "%s\n", mem_buffer);  in calculate_dimm_size()
1085 		edac_dbg(2, "%s\n", mem_buffer);  in calculate_dimm_size()
1095 	edac_dbg(2, "%s\n", mem_buffer);  in calculate_dimm_size()
1108 	edac_dbg(2, "%s\n", mem_buffer);  in calculate_dimm_size()
1121 	edac_dbg(2, "%s\n", mem_buffer);  in calculate_dimm_size()
1146 	edac_dbg(2, "AMBASE= 0x%lx  MAXCH= %d  MAX-DIMM-Per-CH= %d\n",  in i5000_get_mc_regs()
1152 	edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",  in i5000_get_mc_regs()
1156 	edac_dbg(2, "Actual TOLM byte addr=%u (0x%x)\n",  in i5000_get_mc_regs()
1167 	edac_dbg(2, "MIR0: limit= 0x%x  WAY1= %u  WAY0= %x\n",  in i5000_get_mc_regs()
1172 	edac_dbg(2, "MIR1: limit= 0x%x  WAY1= %u  WAY0= %x\n",  in i5000_get_mc_regs()
1177 	edac_dbg(2, "MIR2: limit= 0x%x  WAY1= %u  WAY0= %x\n",  in i5000_get_mc_regs()
1187 		edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",  in i5000_get_mc_regs()
1193 			edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",  in i5000_get_mc_regs()
1201 	edac_dbg(2, "Memory Technology Registers:\n");  in i5000_get_mc_regs()
1202 	edac_dbg(2, "   Branch 0:\n");  in i5000_get_mc_regs()
1208 	edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);  in i5000_get_mc_regs()
1211 	edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);  in i5000_get_mc_regs()
1219 		edac_dbg(2, "   Branch 1:\n");  in i5000_get_mc_regs()
1225 		edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",  in i5000_get_mc_regs()
1229 		edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",  in i5000_get_mc_regs()
1362 	edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",  in i5000_probe1()
1386 	edac_dbg(0, "MC: Number of Branches=2 Channels= %d  DIMMS= %d\n",  in i5000_probe1()
1404 	edac_dbg(0, "MC: mci = %p\n", mci);  in i5000_probe1()
1435 …edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5000_init_csrows() returned nonz…  in i5000_probe1()
1438 		edac_dbg(1, "MC: Enable error reporting now\n");  in i5000_probe1()
1444 		edac_dbg(0, "MC: failed edac_mc_add_mc()\n");  in i5000_probe1()
1487 	edac_dbg(0, "MC:\n");  in i5000_init_one()
1506 	edac_dbg(0, "\n");  in i5000_remove_one()
1552 	edac_dbg(2, "MC:\n");  in i5000_init()
1568 	edac_dbg(2, "MC:\n");  in i5000_exit()