232 	if (pvt->umc) {  in __set_scrub_rate()
274 	if (pvt->umc) {  in get_scrub_rate()
1076 static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)  in umc_normaddr_to_sysaddr()  argument
1096 	ctx.inst_id = umc;  in umc_normaddr_to_sysaddr()
1099 	if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp))  in umc_normaddr_to_sysaddr()
1113 	if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp))  in umc_normaddr_to_sysaddr()
1136 	if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp))  in umc_normaddr_to_sysaddr()
1192 		if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp))  in umc_normaddr_to_sysaddr()
1292 	if (pvt->umc) {  in determine_edac_cap()
1296 			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))  in determine_edac_cap()
1302 			if (pvt->umc[i].umc_cfg & BIT(12))  in determine_edac_cap()
1418 	struct amd64_umc *umc;  in __dump_misc_regs_df()  local
1423 		umc = &pvt->umc[i];  in __dump_misc_regs_df()
1425 		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);  in __dump_misc_regs_df()
1426 		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);  in __dump_misc_regs_df()
1427 		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);  in __dump_misc_regs_df()
1428 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);  in __dump_misc_regs_df()
1435 		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);  in __dump_misc_regs_df()
1438 				i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",  in __dump_misc_regs_df()
1439 				    (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");  in __dump_misc_regs_df()
1441 				i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");  in __dump_misc_regs_df()
1443 				i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");  in __dump_misc_regs_df()
1445 				i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");  in __dump_misc_regs_df()
1447 		if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) {  in __dump_misc_regs_df()
1499 	if (pvt->umc)  in dump_misc_regs()
1521 		int umc;  in prep_chip_selects()  local
1523 		for_each_umc(umc) {  in prep_chip_selects()
1524 			pvt->csels[umc].b_cnt = 4;  in prep_chip_selects()
1525 			pvt->csels[umc].m_cnt = fam_type->flags.zn_regs_v2 ? 4 : 2;  in prep_chip_selects()
1542 	int cs, umc;  in read_umc_base_mask()  local
1544 	for_each_umc(umc) {  in read_umc_base_mask()
1545 		umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;  in read_umc_base_mask()
1546 		umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;  in read_umc_base_mask()
1548 		for_each_chip_select(cs, umc, pvt) {  in read_umc_base_mask()
1549 			base = &pvt->csels[umc].csbases[cs];  in read_umc_base_mask()
1550 			base_sec = &pvt->csels[umc].csbases_sec[cs];  in read_umc_base_mask()
1557 					 umc, cs, *base, base_reg);  in read_umc_base_mask()
1561 					 umc, cs, *base_sec, base_reg_sec);  in read_umc_base_mask()
1564 		umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;  in read_umc_base_mask()
1565 		umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(UMCCH_ADDR_MASK_SEC);  in read_umc_base_mask()
1567 		for_each_chip_select_mask(cs, umc, pvt) {  in read_umc_base_mask()
1568 			mask = &pvt->csels[umc].csmasks[cs];  in read_umc_base_mask()
1569 			mask_sec = &pvt->csels[umc].csmasks_sec[cs];  in read_umc_base_mask()
1576 					 umc, cs, *mask, mask_reg);  in read_umc_base_mask()
1580 					 umc, cs, *mask_sec, mask_reg_sec);  in read_umc_base_mask()
1594 	if (pvt->umc)  in read_dct_base_mask()
1638 	struct amd64_umc *umc;  in determine_memory_type_df()  local
1642 		umc = &pvt->umc[i];  in determine_memory_type_df()
1644 		if (!(umc->sdp_ctrl & UMC_SDP_INIT)) {  in determine_memory_type_df()
1645 			umc->dram_type = MEM_EMPTY;  in determine_memory_type_df()
1653 		if (fam_type->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {  in determine_memory_type_df()
1654 			if (umc->dimm_cfg & BIT(5))  in determine_memory_type_df()
1655 				umc->dram_type = MEM_LRDDR5;  in determine_memory_type_df()
1656 			else if (umc->dimm_cfg & BIT(4))  in determine_memory_type_df()
1657 				umc->dram_type = MEM_RDDR5;  in determine_memory_type_df()
1659 				umc->dram_type = MEM_DDR5;  in determine_memory_type_df()
1661 			if (umc->dimm_cfg & BIT(5))  in determine_memory_type_df()
1662 				umc->dram_type = MEM_LRDDR4;  in determine_memory_type_df()
1663 			else if (umc->dimm_cfg & BIT(4))  in determine_memory_type_df()
1664 				umc->dram_type = MEM_RDDR4;  in determine_memory_type_df()
1666 				umc->dram_type = MEM_DDR4;  in determine_memory_type_df()
1669 		edac_dbg(1, "  UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]);  in determine_memory_type_df()
1677 	if (pvt->umc)  in determine_memory_type()
2060 		channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);  in f17_early_channel_count()
2194 static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,  in f17_addr_mask_to_cs_size()  argument
2239 		addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];  in f17_addr_mask_to_cs_size()
2241 		addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];  in f17_addr_mask_to_cs_size()
3324 	if (pvt->umc) {  in reserve_mc_sibling_devs()
3379 	if (pvt->umc) {  in free_mc_sibling_devs()
3392 	if (pvt->umc) {  in determine_ecc_sym_sz()
3397 			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {  in determine_ecc_sym_sz()
3398 				if (pvt->umc[i].ecc_ctrl & BIT(9)) {  in determine_ecc_sym_sz()
3401 				} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {  in determine_ecc_sym_sz()
3427 	struct amd64_umc *umc;  in __read_mc_regs_df()  local
3434 		umc = &pvt->umc[i];  in __read_mc_regs_df()
3436 		amd_smn_read(nid, umc_base + get_umc_reg(UMCCH_DIMM_CFG), &umc->dimm_cfg);  in __read_mc_regs_df()
3437 		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);  in __read_mc_regs_df()
3438 		amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);  in __read_mc_regs_df()
3439 		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);  in __read_mc_regs_df()
3440 		amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);  in __read_mc_regs_df()
3469 	if (pvt->umc) {  in read_mc_regs()
3521 	if (!pvt->umc)  in read_mc_regs()
3567 	if (!pvt->umc) {  in get_csrow_nr_pages()
3591 	u8 umc, cs;  in init_csrows_df()  local
3606 	for_each_umc(umc) {  in init_csrows_df()
3607 		for_each_chip_select(cs, umc, pvt) {  in init_csrows_df()
3608 			if (!csrow_enabled(cs, umc, pvt))  in init_csrows_df()
3612 			dimm = mci->csrows[cs]->channels[umc]->dimm;  in init_csrows_df()
3617 			dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs);  in init_csrows_df()
3618 			dimm->mtype = pvt->umc[umc].dram_type;  in init_csrows_df()
3642 	if (pvt->umc)  in init_csrows()
3874 		struct amd64_umc *umc;  in ecc_enabled()  local
3877 			umc = &pvt->umc[i];  in ecc_enabled()
3880 			if (!(umc->sdp_ctrl & UMC_SDP_INIT))  in ecc_enabled()
3885 			if (umc->umc_cap_hi & UMC_ECC_ENABLED)  in ecc_enabled()
3922 		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {  in f17h_determine_edac_ctl_cap()
3923 			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);  in f17h_determine_edac_ctl_cap()
3924 			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);  in f17h_determine_edac_ctl_cap()
3926 			dev_x4  &= !!(pvt->umc[i].dimm_cfg & BIT(6));  in f17h_determine_edac_ctl_cap()
3927 			dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));  in f17h_determine_edac_ctl_cap()
3954 	if (pvt->umc) {  in setup_mci_misc_attrs()
4099 		pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);  in hw_info_get()
4100 		if (!pvt->umc)  in hw_info_get()
4124 	kfree(pvt->umc);  in hw_info_put()