390 	edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",  in find_mc_by_sys_addr()
489 			edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",  in input_addr_to_csrow()
496 	edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",  in input_addr_to_csrow()
525 		edac_dbg(1, "  revision %d for node %d does not support DHAR\n",  in get_dram_hole_info()
532 		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this system\n");  in get_dram_hole_info()
537 		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this node %d\n",  in get_dram_hole_info()
566 	edac_dbg(1, "  DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",  in get_dram_hole_info()
762 	edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);  in inject_read_store()
811 	edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);  in inject_write_store()
898 			edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",  in sys_addr_to_dram_addr()
917 	edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",  in sys_addr_to_dram_addr()
954 	edac_dbg(2, "  Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",  in dram_addr_to_input_addr()
972 	edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",  in sys_addr_to_input_addr()
1324 	edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);  in debug_dump_dramcfg_low()
1333 		edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));  in debug_dump_dramcfg_low()
1336 	edac_dbg(1, "All DIMMs support ECC:%s\n",  in debug_dump_dramcfg_low()
1340 	edac_dbg(1, "  PAR/ERR parity: %s\n",  in debug_dump_dramcfg_low()
1344 		edac_dbg(1, "  DCT 128bit mode width: %s\n",  in debug_dump_dramcfg_low()
1347 	edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",  in debug_dump_dramcfg_low()
1388 		edac_dbg(1, "3R interleaving in use.\n");  in f17_get_cs_mode()
1425 		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);  in __dump_misc_regs_df()
1426 		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);  in __dump_misc_regs_df()
1427 		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);  in __dump_misc_regs_df()
1428 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);  in __dump_misc_regs_df()
1431 		edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);  in __dump_misc_regs_df()
1434 		edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);  in __dump_misc_regs_df()
1435 		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);  in __dump_misc_regs_df()
1437 		edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",  in __dump_misc_regs_df()
1440 		edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",  in __dump_misc_regs_df()
1442 		edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",  in __dump_misc_regs_df()
1444 		edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",  in __dump_misc_regs_df()
1451 			edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",  in __dump_misc_regs_df()
1458 	edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",  in __dump_misc_regs_df()
1465 	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);  in __dump_misc_regs()
1467 	edac_dbg(1, "  NB two channel DRAM capable: %s\n",  in __dump_misc_regs()
1470 	edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",  in __dump_misc_regs()
1476 	edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);  in __dump_misc_regs()
1478 	edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",  in __dump_misc_regs()
1504 	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");  in dump_misc_regs()
1556 				edac_dbg(0, "  DCSB%d[%d]=0x%08x reg: 0x%x\n",  in read_umc_base_mask()
1560 				edac_dbg(0, "    DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n",  in read_umc_base_mask()
1575 				edac_dbg(0, "  DCSM%d[%d]=0x%08x reg: 0x%x\n",  in read_umc_base_mask()
1579 				edac_dbg(0, "    DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n",  in read_umc_base_mask()
1604 			edac_dbg(0, "  DCSB0[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1611 			edac_dbg(0, "  DCSB1[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1623 			edac_dbg(0, "    DCSM0[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1630 			edac_dbg(0, "    DCSM1[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1669 		edac_dbg(1, "  UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]);  in determine_memory_type_df()
2028 	edac_dbg(0, "Data width is not 128 bits - need more decoding\n");  in f1x_early_channel_count()
2261 	edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);  in f17_addr_mask_to_cs_size()
2262 	edac_dbg(1, "  Original AddrMask: 0x%x\n", addr_mask_orig);  in f17_addr_mask_to_cs_size()
2263 	edac_dbg(1, "  Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved);  in f17_addr_mask_to_cs_size()
2279 		edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",  in read_dram_ctl_register()
2282 		edac_dbg(0, "  DCTs operate in %s mode\n",  in read_dram_ctl_register()
2286 			edac_dbg(0, "  Address range split per DCT: %s\n",  in read_dram_ctl_register()
2289 		edac_dbg(0, "  data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",  in read_dram_ctl_register()
2293 		edac_dbg(0, "  channel interleave: %s, "  in read_dram_ctl_register()
2471 	edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);  in f1x_lookup_addr_in_dct()
2479 		edac_dbg(1, "    CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",  in f1x_lookup_addr_in_dct()
2484 		edac_dbg(1, "    (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",  in f1x_lookup_addr_in_dct()
2494 			edac_dbg(1, " MATCH csrow=%d\n", cs_found);  in f1x_lookup_addr_in_dct()
2549 	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",  in f1x_match_to_this_node()
2606 	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);  in f1x_match_to_this_node()
2637 	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",  in f15_m30h_match_to_this_node()
2718 	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);  in f15_m30h_match_to_this_node()
2822 	edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",  in debug_display_dimm_sizes()
3115 	edac_dbg(0, "syndrome(%x) not found\n", syndrome);  in decode_syndrome()
3327 			edac_dbg(1, "F0 not found, device 0x%x\n", pci_id1);  in reserve_mc_sibling_devs()
3336 			edac_dbg(1, "F6 not found: device 0x%x\n", pci_id2);  in reserve_mc_sibling_devs()
3343 		edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));  in reserve_mc_sibling_devs()
3344 		edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));  in reserve_mc_sibling_devs()
3345 		edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));  in reserve_mc_sibling_devs()
3353 		edac_dbg(1, "F1 not found: device 0x%x\n", pci_id1);  in reserve_mc_sibling_devs()
3363 		edac_dbg(1, "F2 not found: device 0x%x\n", pci_id2);  in reserve_mc_sibling_devs()
3370 	edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));  in reserve_mc_sibling_devs()
3371 	edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));  in reserve_mc_sibling_devs()
3372 	edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));  in reserve_mc_sibling_devs()
3458 	edac_dbg(0, "  TOP_MEM:  0x%016llx\n", pvt->top_mem);  in read_mc_regs()
3464 		edac_dbg(0, "  TOP_MEM2: 0x%016llx\n", pvt->top_mem2);  in read_mc_regs()
3466 		edac_dbg(0, "  TOP_MEM2 disabled\n");  in read_mc_regs()
3490 		edac_dbg(1, "  DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",  in read_mc_regs()
3495 		edac_dbg(1, "   IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",  in read_mc_regs()
3522 		edac_dbg(1, "  DIMM type: %s\n", edac_mem_types[pvt->dram_type]);  in read_mc_regs()
3577 	edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",  in get_csrow_nr_pages()
3579 	edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);  in get_csrow_nr_pages()
3614 			edac_dbg(1, "MC node: %d, csrow: %d\n",  in init_csrows_df()
3649 	edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",  in init_csrows()
3669 		edac_dbg(1, "MC node: %d, csrow: %d\n",  in init_csrows()
3685 		edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);  in init_csrows()
3735 		edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",  in nb_mce_bank_enabled_on_node()
3808 	edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",  in enable_ecc_error_reporting()
3833 	edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",  in enable_ecc_error_reporting()
3893 			edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);  in ecc_enabled()
3904 			edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",  in ecc_enabled()
3908 	edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));  in ecc_enabled()
4170 		edac_dbg(1, "failed edac_mc_add_mc()\n");  in init_one_instance()