205 	struct tegra_dma_channel_regs ch_regs;  member
470 	struct tegra_dma_channel_regs *ch_regs;  in tegra_dma_configure_next_sg()  local
489 	ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;  in tegra_dma_configure_next_sg()
491 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);  in tegra_dma_configure_next_sg()
492 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);  in tegra_dma_configure_next_sg()
493 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);  in tegra_dma_configure_next_sg()
494 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);  in tegra_dma_configure_next_sg()
498 		  ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);  in tegra_dma_configure_next_sg()
504 	struct tegra_dma_channel_regs *ch_regs;  in tegra_dma_start()  local
520 	ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;  in tegra_dma_start()
522 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);  in tegra_dma_start()
524 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);  in tegra_dma_start()
525 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);  in tegra_dma_start()
526 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);  in tegra_dma_start()
527 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);  in tegra_dma_start()
528 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);  in tegra_dma_start()
529 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);  in tegra_dma_start()
530 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);  in tegra_dma_start()
534 		  ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);  in tegra_dma_start()
902 	sg_req[0].ch_regs.src_ptr = 0;  in tegra_dma_prep_dma_memset()
903 	sg_req[0].ch_regs.dst_ptr = dest;  in tegra_dma_prep_dma_memset()
904 	sg_req[0].ch_regs.high_addr_ptr =  in tegra_dma_prep_dma_memset()
906 	sg_req[0].ch_regs.fixed_pattern = value;  in tegra_dma_prep_dma_memset()
908 	sg_req[0].ch_regs.wcount = ((len - 4) >> 2);  in tegra_dma_prep_dma_memset()
909 	sg_req[0].ch_regs.csr = csr;  in tegra_dma_prep_dma_memset()
910 	sg_req[0].ch_regs.mmio_seq = 0;  in tegra_dma_prep_dma_memset()
911 	sg_req[0].ch_regs.mc_seq = mc_seq;  in tegra_dma_prep_dma_memset()
971 	sg_req[0].ch_regs.src_ptr = src;  in tegra_dma_prep_dma_memcpy()
972 	sg_req[0].ch_regs.dst_ptr = dest;  in tegra_dma_prep_dma_memcpy()
973 	sg_req[0].ch_regs.high_addr_ptr =  in tegra_dma_prep_dma_memcpy()
975 	sg_req[0].ch_regs.high_addr_ptr |=  in tegra_dma_prep_dma_memcpy()
978 	sg_req[0].ch_regs.wcount = ((len - 4) >> 2);  in tegra_dma_prep_dma_memcpy()
979 	sg_req[0].ch_regs.csr = csr;  in tegra_dma_prep_dma_memcpy()
980 	sg_req[0].ch_regs.mmio_seq = 0;  in tegra_dma_prep_dma_memcpy()
981 	sg_req[0].ch_regs.mc_seq = mc_seq;  in tegra_dma_prep_dma_memcpy()
1082 			sg_req[i].ch_regs.src_ptr = mem;  in tegra_dma_prep_slave_sg()
1083 			sg_req[i].ch_regs.dst_ptr = apb_ptr;  in tegra_dma_prep_slave_sg()
1084 			sg_req[i].ch_regs.high_addr_ptr =  in tegra_dma_prep_slave_sg()
1087 			sg_req[i].ch_regs.src_ptr = apb_ptr;  in tegra_dma_prep_slave_sg()
1088 			sg_req[i].ch_regs.dst_ptr = mem;  in tegra_dma_prep_slave_sg()
1089 			sg_req[i].ch_regs.high_addr_ptr =  in tegra_dma_prep_slave_sg()
1097 		sg_req[i].ch_regs.wcount = ((len - 4) >> 2);  in tegra_dma_prep_slave_sg()
1098 		sg_req[i].ch_regs.csr = csr;  in tegra_dma_prep_slave_sg()
1099 		sg_req[i].ch_regs.mmio_seq = mmio_seq;  in tegra_dma_prep_slave_sg()
1100 		sg_req[i].ch_regs.mc_seq = mc_seq;  in tegra_dma_prep_slave_sg()
1204 			sg_req[i].ch_regs.src_ptr = mem;  in tegra_dma_prep_dma_cyclic()
1205 			sg_req[i].ch_regs.dst_ptr = apb_ptr;  in tegra_dma_prep_dma_cyclic()
1206 			sg_req[i].ch_regs.high_addr_ptr =  in tegra_dma_prep_dma_cyclic()
1209 			sg_req[i].ch_regs.src_ptr = apb_ptr;  in tegra_dma_prep_dma_cyclic()
1210 			sg_req[i].ch_regs.dst_ptr = mem;  in tegra_dma_prep_dma_cyclic()
1211 			sg_req[i].ch_regs.high_addr_ptr =  in tegra_dma_prep_dma_cyclic()
1218 		sg_req[i].ch_regs.wcount = ((len - 4) >> 2);  in tegra_dma_prep_dma_cyclic()
1219 		sg_req[i].ch_regs.csr = csr;  in tegra_dma_prep_dma_cyclic()
1220 		sg_req[i].ch_regs.mmio_seq = mmio_seq;  in tegra_dma_prep_dma_cyclic()
1221 		sg_req[i].ch_regs.mc_seq = mc_seq;  in tegra_dma_prep_dma_cyclic()