280 static struct device *chan2dev(struct stm32_mdma_chan *chan)  in chan2dev()  function
339 	dev_err(chan2dev(chan), "Failed to allocate descriptor\n");  in stm32_mdma_alloc_desc()
369 		dev_err(chan2dev(chan), "Dma bus width %i not supported\n",  in stm32_mdma_get_width()
427 			dev_err(chan2dev(chan), "%s: timeout!\n", __func__);  in stm32_mdma_disable_chan()
449 		dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",  in stm32_mdma_stop()
518 		dev_err(chan2dev(chan),  in stm32_mdma_set_xfer_param()
526 		dev_err(chan2dev(chan), "burst size must be a power of 2\n");  in stm32_mdma_set_xfer_param()
663 		dev_err(chan2dev(chan), "Dma direction is not supported\n");  in stm32_mdma_set_xfer_param()
677 	dev_dbg(chan2dev(chan), "hwdesc:  %pad\n", &node->hwdesc_phys);  in stm32_mdma_dump_hwdesc()
678 	dev_dbg(chan2dev(chan), "CTCR:    0x%08x\n", node->hwdesc->ctcr);  in stm32_mdma_dump_hwdesc()
679 	dev_dbg(chan2dev(chan), "CBNDTR:  0x%08x\n", node->hwdesc->cbndtr);  in stm32_mdma_dump_hwdesc()
680 	dev_dbg(chan2dev(chan), "CSAR:    0x%08x\n", node->hwdesc->csar);  in stm32_mdma_dump_hwdesc()
681 	dev_dbg(chan2dev(chan), "CDAR:    0x%08x\n", node->hwdesc->cdar);  in stm32_mdma_dump_hwdesc()
682 	dev_dbg(chan2dev(chan), "CBRUR:   0x%08x\n", node->hwdesc->cbrur);  in stm32_mdma_dump_hwdesc()
683 	dev_dbg(chan2dev(chan), "CLAR:    0x%08x\n", node->hwdesc->clar);  in stm32_mdma_dump_hwdesc()
684 	dev_dbg(chan2dev(chan), "CTBR:    0x%08x\n", node->hwdesc->ctbr);  in stm32_mdma_dump_hwdesc()
685 	dev_dbg(chan2dev(chan), "CMAR:    0x%08x\n", node->hwdesc->cmar);  in stm32_mdma_dump_hwdesc()
686 	dev_dbg(chan2dev(chan), "CMDR:    0x%08x\n\n", node->hwdesc->cmdr);  in stm32_mdma_dump_hwdesc()
744 			dev_err(chan2dev(chan), "Invalid block len\n");  in stm32_mdma_setup_xfer()
804 		dev_err(chan2dev(chan),  in stm32_mdma_prep_slave_sg()
865 		dev_err(chan2dev(chan),  in stm32_mdma_prep_dma_cyclic()
871 		dev_err(chan2dev(chan), "Invalid buffer/period len\n");  in stm32_mdma_prep_dma_cyclic()
876 		dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");  in stm32_mdma_prep_dma_cyclic()
961 		dev_err(chan2dev(chan),  in stm32_mdma_prep_dma_memcpy()
1123 	dev_dbg(chan2dev(chan), "CCR:     0x%08x\n",  in stm32_mdma_dump_reg()
1125 	dev_dbg(chan2dev(chan), "CTCR:    0x%08x\n",  in stm32_mdma_dump_reg()
1127 	dev_dbg(chan2dev(chan), "CBNDTR:  0x%08x\n",  in stm32_mdma_dump_reg()
1129 	dev_dbg(chan2dev(chan), "CSAR:    0x%08x\n",  in stm32_mdma_dump_reg()
1131 	dev_dbg(chan2dev(chan), "CDAR:    0x%08x\n",  in stm32_mdma_dump_reg()
1133 	dev_dbg(chan2dev(chan), "CBRUR:   0x%08x\n",  in stm32_mdma_dump_reg()
1135 	dev_dbg(chan2dev(chan), "CLAR:    0x%08x\n",  in stm32_mdma_dump_reg()
1137 	dev_dbg(chan2dev(chan), "CTBR:    0x%08x\n",  in stm32_mdma_dump_reg()
1139 	dev_dbg(chan2dev(chan), "CMAR:    0x%08x\n",  in stm32_mdma_dump_reg()
1141 	dev_dbg(chan2dev(chan), "CMDR:    0x%08x\n",  in stm32_mdma_dump_reg()
1194 	dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);  in stm32_mdma_start_transfer()
1207 	dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);  in stm32_mdma_issue_pending()
1227 		dev_dbg(chan2dev(chan), "vchan %pK: pause\n", &chan->vchan);  in stm32_mdma_pause()
1264 	dev_dbg(chan2dev(chan), "vchan %pK: resume\n", &chan->vchan);  in stm32_mdma_resume()
1412 			dev_warn(chan2dev(chan),  in stm32_mdma_irq_handler()
1415 			dev_dbg(chan2dev(chan),  in stm32_mdma_irq_handler()
1423 		dev_err(chan2dev(chan), "Transfer Err: stat=0x%08x\n",  in stm32_mdma_irq_handler()
1458 		dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);  in stm32_mdma_irq_handler()
1460 			dev_err(chan2dev(chan), "chan disabled by HW\n");  in stm32_mdma_irq_handler()
1480 		dev_err(chan2dev(chan), "failed to allocate descriptor pool\n");  in stm32_mdma_alloc_chan_resources()
1501 	dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);  in stm32_mdma_free_chan_resources()