309 	writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |  in ni_pcidio_request_di_mite_channel()
325 		writeb(primary_DMAChannel_bits(0) |  in ni_pcidio_release_di_mite_channel()
407 			writeb(0x00,  in nidio_interrupt()
420 					writeb(0x00, dev->mmio +  in nidio_interrupt()
432 			writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR);  in nidio_interrupt()
435 			writeb(0x00, dev->mmio + OP_MODE);  in nidio_interrupt()
438 			writeb(CLEAR_WAITED, dev->mmio + GROUP_1_FIRST_CLEAR);  in nidio_interrupt()
442 			writeb(CLEAR_PRIMARY_TC,  in nidio_interrupt()
446 			writeb(CLEAR_SECONDARY_TC,  in nidio_interrupt()
459 		writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);  in nidio_interrupt()
611 	writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);  in ni_pcidio_inttrig()
627 		writeb(0x0f, dev->mmio + DATA_PATH);  in ni_pcidio_cmd()
630 		writeb(TRANSFER_WIDTH(0) | TRANSFER_LENGTH(0),  in ni_pcidio_cmd()
633 		writeb(0x03, dev->mmio + DATA_PATH);  in ni_pcidio_cmd()
634 		writeb(TRANSFER_WIDTH(3) | TRANSFER_LENGTH(0),  in ni_pcidio_cmd()
641 		writeb(0, dev->mmio + OP_MODE);  in ni_pcidio_cmd()
642 		writeb(0x00, dev->mmio + CLOCK_REG);  in ni_pcidio_cmd()
643 		writeb(1, dev->mmio + SEQUENCE);  in ni_pcidio_cmd()
644 		writeb(0x04, dev->mmio + REQ_REG);  in ni_pcidio_cmd()
645 		writeb(4, dev->mmio + BLOCK_MODE);  in ni_pcidio_cmd()
646 		writeb(3, dev->mmio + LINE_POLARITIES);  in ni_pcidio_cmd()
647 		writeb(0xc0, dev->mmio + ACK_SER);  in ni_pcidio_cmd()
651 		writeb(1, dev->mmio + REQ_DELAY);  in ni_pcidio_cmd()
652 		writeb(1, dev->mmio + REQ_NOT_DELAY);  in ni_pcidio_cmd()
653 		writeb(1, dev->mmio + ACK_DELAY);  in ni_pcidio_cmd()
654 		writeb(0x0b, dev->mmio + ACK_NOT_DELAY);  in ni_pcidio_cmd()
655 		writeb(0x01, dev->mmio + DATA_1_DELAY);  in ni_pcidio_cmd()
661 		writeb(0, dev->mmio + DAQ_OPTIONS);  in ni_pcidio_cmd()
665 		writeb(0, dev->mmio + OP_MODE);  in ni_pcidio_cmd()
666 		writeb(0x00, dev->mmio + CLOCK_REG);  in ni_pcidio_cmd()
667 		writeb(0, dev->mmio + SEQUENCE);  in ni_pcidio_cmd()
668 		writeb(0x00, dev->mmio + REQ_REG);  in ni_pcidio_cmd()
669 		writeb(4, dev->mmio + BLOCK_MODE);  in ni_pcidio_cmd()
671 			writeb(0, dev->mmio + LINE_POLARITIES);  in ni_pcidio_cmd()
673 			writeb(2, dev->mmio + LINE_POLARITIES);  in ni_pcidio_cmd()
674 		writeb(0x00, dev->mmio + ACK_SER);  in ni_pcidio_cmd()
676 		writeb(1, dev->mmio + REQ_DELAY);  in ni_pcidio_cmd()
677 		writeb(1, dev->mmio + REQ_NOT_DELAY);  in ni_pcidio_cmd()
678 		writeb(1, dev->mmio + ACK_DELAY);  in ni_pcidio_cmd()
679 		writeb(0x0C, dev->mmio + ACK_NOT_DELAY);  in ni_pcidio_cmd()
680 		writeb(0x10, dev->mmio + DATA_1_DELAY);  in ni_pcidio_cmd()
682 		writeb(0x60, dev->mmio + DAQ_OPTIONS);  in ni_pcidio_cmd()
693 	writeb(CLEAR_PRIMARY_TC | CLEAR_SECONDARY_TC,  in ni_pcidio_cmd()
703 	writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP1);  in ni_pcidio_cmd()
705 	writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP2);  in ni_pcidio_cmd()
708 	writeb(0xff, dev->mmio + GROUP_1_FIRST_CLEAR);  in ni_pcidio_cmd()
711 	writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL);  in ni_pcidio_cmd()
712 	writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);  in ni_pcidio_cmd()
721 		writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);  in ni_pcidio_cmd()
734 	writeb(0x00, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);  in ni_pcidio_cancel()
876 	writeb(0, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);  in nidio_reset_board()