Lines Matching refs:PLL_DIV
112 #define PLL_DIV(x) ((x) + 0x04) macro
193 LGM_DIV(LGM_CLK_PP_HW, "pp_hw", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
195 LGM_DIV(LGM_CLK_PP_UC, "pp_uc", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
197 LGM_DIV(LGM_CLK_PP_FXD, "pp_fxd", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
199 LGM_DIV(LGM_CLK_PP_TBM, "pp_tbm", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
202 PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
204 LGM_DIV(LGM_CLK_CM, "cpu_cm", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
208 PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
211 LGM_DIV(LGM_CLK_SDXC3, "sdxc3", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
215 CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
218 CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM1_CFG0),
228 (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
231 (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
233 LGM_DIV(LGM_CLK_SW, "switch", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
235 LGM_DIV(LGM_CLK_QSPI, "qspi", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
237 LGM_DIV(LGM_CLK_CT, "v_ct", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
239 LGM_DIV(LGM_CLK_DSP, "v_dsp", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
241 LGM_DIV(LGM_CLK_VIF, "v_ifclk", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
406 PLL_DIV(CGU_LJPLL3_CFG0), 0, PLL_DDIV_WIDTH,
409 PLL_DIV(CGU_LJPLL3_CFG0), 6, PLL_DDIV_WIDTH,
412 PLL_DIV(CGU_LJPLL3_CFG0), 12, PLL_DDIV_WIDTH,
415 PLL_DIV(CGU_LJPLL3_CFG0), 18, PLL_DDIV_WIDTH,
418 PLL_DIV(CGU_LJPLL4_CFG0), 0, PLL_DDIV_WIDTH,