49 	u32 divider;		/* Cached divider value */  member
85 		  cdesc->divider - 1);  in atl_clk_enable()
120 	return parent_rate / cdesc->divider;  in atl_clk_recalc_rate()
126 	unsigned divider;  in atl_clk_round_rate()  local
128 	divider = (*parent_rate + rate / 2) / rate;  in atl_clk_round_rate()
129 	if (divider > DRA7_ATL_DIVIDER_MASK + 1)  in atl_clk_round_rate()
130 		divider = DRA7_ATL_DIVIDER_MASK + 1;  in atl_clk_round_rate()
132 	return *parent_rate / divider;  in atl_clk_round_rate()
139 	u32 divider;  in atl_clk_set_rate()  local
145 	divider = ((parent_rate + rate / 2) / rate) - 1;  in atl_clk_set_rate()
146 	if (divider > DRA7_ATL_DIVIDER_MASK)  in atl_clk_set_rate()
147 		divider = DRA7_ATL_DIVIDER_MASK;  in atl_clk_set_rate()
149 	cdesc->divider = divider + 1;  in atl_clk_set_rate()
178 	clk_hw->divider = 1;  in of_dra7_atl_clock_setup()