Lines Matching refs:TI_CLK_GATE

292 	{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
293 	{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
294 	{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
295 	{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
296 	{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
297 	{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
349 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
366 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
378 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
388 	{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
393 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
421 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
422 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
423 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
428 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
429 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
430 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
512 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
517 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
522 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
527 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
532 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
537 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
542 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
557 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
574 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
782 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },