Lines Matching refs:TI_CLK_MUX
67 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
68 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
80 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
81 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
93 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
94 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
106 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
107 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
118 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
123 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
128 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
133 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
201 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
206 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
211 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
216 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
221 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
226 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
374 { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
375 { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
402 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
417 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
464 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
465 { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
514 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },