526 	for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)  in _get_table_rate()
527 		if (sel->input_rate == parent_rate &&  in _get_table_rate()
531 	if (sel->input_rate == 0)  in _get_table_rate()
542 	cfg->input_rate = sel->input_rate;  in _get_table_rate()
959 	unsigned long input_rate;  in clk_plle_enable()  local
966 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));  in clk_plle_enable()
968 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_enable()
1122 	unsigned long flags = 0, input_rate;  in clk_pllu_enable()  local
1132 	input_rate = clk_hw_get_rate(osc);  in clk_pllu_enable()
1145 		if (input_rate == utmi_parameters[i].osc_frequency) {  in clk_pllu_enable()
1153 		       input_rate);  in clk_pllu_enable()
1235 	cfg->input_rate = parent_rate;  in _calc_dynamic_ramp_rate()
1254 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)  in tegra_pll_get_fixed_mdiv()  argument
1258 	return (u16)_pll_fixed_mdiv(pll->params, input_rate);  in tegra_pll_get_fixed_mdiv()
1453 					unsigned long input_rate, u32 n)  in _pllcx_update_dynamic_coef()  argument
1457 	switch (input_rate) {  in _pllcx_update_dynamic_coef()
1473 			__func__, input_rate);  in _pllcx_update_dynamic_coef()
1616 	unsigned long input_rate;  in clk_plle_tegra114_enable()  local
1618 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));  in clk_plle_tegra114_enable()
1620 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_tegra114_enable()
1745 	unsigned long flags = 0, input_rate;  in clk_pllu_tegra114_enable()  local
1755 	input_rate = clk_hw_get_rate(__clk_get_hw(osc));  in clk_pllu_tegra114_enable()
1768 		if (input_rate == utmi_parameters[i].osc_frequency) {  in clk_pllu_tegra114_enable()
1776 		       input_rate);  in clk_pllu_tegra114_enable()
2455 	unsigned long input_rate;  in clk_plle_tegra210_enable()  local
2460 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));  in clk_plle_tegra210_enable()
2462 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_tegra210_enable()