210 	const struct stm32_div_cfg *divider = &data->dividers[div_id];  in stm32_divider_get_rate()  local
214 	val =  readl(base + divider->offset) >> divider->shift;  in stm32_divider_get_rate()
215 	val &= clk_div_mask(divider->width);  in stm32_divider_get_rate()
216 	div = _get_div(divider->table, val, divider->flags, divider->width);  in stm32_divider_get_rate()
219 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),  in stm32_divider_get_rate()
233 	const struct stm32_div_cfg *divider = &data->dividers[div_id];  in stm32_divider_set_rate()  local
237 	value = divider_get_val(rate, parent_rate, divider->table,  in stm32_divider_set_rate()
238 				divider->width, divider->flags);  in stm32_divider_set_rate()
242 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in stm32_divider_set_rate()
243 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in stm32_divider_set_rate()
245 		val = readl(base + divider->offset);  in stm32_divider_set_rate()
246 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in stm32_divider_set_rate()
249 	val |= (u32)value << divider->shift;  in stm32_divider_set_rate()
251 	writel(val, base + divider->offset);  in stm32_divider_set_rate()
355 	const struct stm32_div_cfg *divider;  in clk_stm32_divider_round_rate()  local
360 	divider = &div->clock_data->dividers[div->div_id];  in clk_stm32_divider_round_rate()
363 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_stm32_divider_round_rate()
366 		val =  readl(div->base + divider->offset) >> divider->shift;  in clk_stm32_divider_round_rate()
367 		val &= clk_div_mask(divider->width);  in clk_stm32_divider_round_rate()
369 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in clk_stm32_divider_round_rate()
370 				divider->width, divider->flags,  in clk_stm32_divider_round_rate()
375 					 rate, prate, divider->table,  in clk_stm32_divider_round_rate()
376 					 divider->width, divider->flags);  in clk_stm32_divider_round_rate()
433 	const struct stm32_div_cfg *divider;  in clk_stm32_composite_round_rate()  local
438 	divider = &composite->clock_data->dividers[composite->div_id];  in clk_stm32_composite_round_rate()
441 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_stm32_composite_round_rate()
444 		val =  readl(composite->base + divider->offset) >> divider->shift;  in clk_stm32_composite_round_rate()
445 		val &= clk_div_mask(divider->width);  in clk_stm32_composite_round_rate()
447 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in clk_stm32_composite_round_rate()
448 				divider->width, divider->flags,  in clk_stm32_composite_round_rate()
453 					 rate, prate, divider->table,  in clk_stm32_composite_round_rate()
454 					 divider->width, divider->flags);  in clk_stm32_composite_round_rate()