46 	struct clkgen_field ndiv;  member
80 	.ndiv		= CLKGEN_FIELD(0x2a4,	C32_NDIV_MASK,		16),
115 	.ndiv		= CLKGEN_FIELD(0x2cc,	C32_NDIV_MASK,		16),
141 	.ndiv		= CLKGEN_FIELD(0x1b0,	C32_NDIV_MASK,		0),
167 	.ndiv		= CLKGEN_FIELD(0x1b0,	C28_NDIV_MASK,		0),
211 	u32 ndiv;  member
220 	unsigned long ndiv;  member
350 			pll->ndiv = n;  in clk_pll3200c32_get_params()
359 	for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)  in clk_pll3200c32_get_params()
371 	*rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;  in clk_pll3200c32_get_rate()
380 	unsigned long ndiv, idf;  in recalc_stm_pll3200c32()  local
386 	ndiv = CLKGEN_READ(pll, ndiv);  in recalc_stm_pll3200c32()
391 		rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;  in recalc_stm_pll3200c32()
413 		 rate, (unsigned int)params.ndiv,  in round_rate_stm_pll3200c32()
435 		 hwrate, (unsigned int)params.ndiv,  in set_rate_stm_pll3200c32()
441 	pll->ndiv = params.ndiv;  in set_rate_stm_pll3200c32()
450 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in set_rate_stm_pll3200c32()
509 				pll->ndiv = n;  in clk_pll4600c28_get_params()
527 	*rate = (input / pll->idf) * 2 * pll->ndiv;  in clk_pll4600c28_get_rate()
542 	params.ndiv = CLKGEN_READ(pll, ndiv);  in recalc_stm_pll4600c28()
567 		 rate, (unsigned int)params.ndiv,  in round_rate_stm_pll4600c28()
594 		 hwrate, (unsigned int)params.ndiv,  in set_rate_stm_pll4600c28()
600 	pll->ndiv = params.ndiv;  in set_rate_stm_pll4600c28()
608 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in set_rate_stm_pll4600c28()