66 static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,  in pll_calc_rate()  argument
72 	mode = rtbl[index].mode ? 256 : 1;  in pll_calc_rate()
73 	rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));  in pll_calc_rate()
76 		*pll_rate = (rate / (1 << rtbl[index].p)) * 10000;  in pll_calc_rate()
97 		*prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,  in clk_pll_round_rate_index()
145 	struct pll_rate_tbl *rtbl = pll->vco->rtbl;  in clk_pll_set_rate()  local
156 	val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;  in clk_pll_set_rate()
176 	return pll_calc_rate(vco->rtbl, prate, index, NULL);  in vco_calc_rate()
231 	struct pll_rate_tbl *rtbl = vco->rtbl;  in clk_vco_set_rate()  local
243 	val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;  in clk_vco_set_rate()
248 	val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;  in clk_vco_set_rate()
251 	if (rtbl[i].mode)  in clk_vco_set_rate()
252 		val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<  in clk_vco_set_rate()
255 		val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<  in clk_vco_set_rate()
275 		*cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,  in clk_register_vco_pll()  argument
286 			!rtbl || !rtbl_cnt) {  in clk_register_vco_pll()
302 	vco->rtbl = rtbl;  in clk_register_vco_pll()