58 static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)  in __prci_wrpll_unpack()  argument
62 	v = r & PRCI_COREPLLCFG0_DIVR_MASK;  in __prci_wrpll_unpack()
66 	v = r & PRCI_COREPLLCFG0_DIVF_MASK;  in __prci_wrpll_unpack()
70 	v = r & PRCI_COREPLLCFG0_DIVQ_MASK;  in __prci_wrpll_unpack()
74 	v = r & PRCI_COREPLLCFG0_RANGE_MASK;  in __prci_wrpll_unpack()
102 	u32 r = 0;  in __prci_wrpll_pack()  local
104 	r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;  in __prci_wrpll_pack()
105 	r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;  in __prci_wrpll_pack()
106 	r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;  in __prci_wrpll_pack()
107 	r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;  in __prci_wrpll_pack()
110 	r |= PRCI_COREPLLCFG0_FSE_MASK;  in __prci_wrpll_pack()
112 	return r;  in __prci_wrpll_pack()
207 	int r;  in sifive_prci_wrpll_set_rate()  local
209 	r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);  in sifive_prci_wrpll_set_rate()
210 	if (r)  in sifive_prci_wrpll_set_rate()
211 		return r;  in sifive_prci_wrpll_set_rate()
228 	u32 r;  in sifive_clk_is_enabled()  local
230 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_clk_is_enabled()
232 	if (r & PRCI_COREPLLCFG1_CKE_MASK)  in sifive_clk_is_enabled()
260 	u32 r;  in sifive_prci_clock_disable()  local
265 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_prci_clock_disable()
266 	r &= ~PRCI_COREPLLCFG1_CKE_MASK;  in sifive_prci_clock_disable()
268 	__prci_wrpll_write_cfg1(pd, pwd, r);  in sifive_prci_clock_disable()
315 	u32 r;  in sifive_prci_coreclksel_use_hfclk()  local
317 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_hfclk()
318 	r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;  in sifive_prci_coreclksel_use_hfclk()
319 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_hfclk()
321 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_hfclk()
336 	u32 r;  in sifive_prci_coreclksel_use_corepll()  local
338 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_corepll()
339 	r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;  in sifive_prci_coreclksel_use_corepll()
340 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_corepll()
342 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_corepll()
358 	u32 r;  in sifive_prci_coreclksel_use_final_corepll()  local
360 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_final_corepll()
361 	r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;  in sifive_prci_coreclksel_use_final_corepll()
362 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_final_corepll()
364 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_final_corepll()
379 	u32 r;  in sifive_prci_corepllsel_use_dvfscorepll()  local
381 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);  in sifive_prci_corepllsel_use_dvfscorepll()
382 	r |= PRCI_COREPLLSEL_COREPLLSEL_MASK;  in sifive_prci_corepllsel_use_dvfscorepll()
383 	__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);  in sifive_prci_corepllsel_use_dvfscorepll()
385 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);	/* barrier */  in sifive_prci_corepllsel_use_dvfscorepll()
400 	u32 r;  in sifive_prci_corepllsel_use_corepll()  local
402 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);  in sifive_prci_corepllsel_use_corepll()
403 	r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK;  in sifive_prci_corepllsel_use_corepll()
404 	__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);  in sifive_prci_corepllsel_use_corepll()
406 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);	/* barrier */  in sifive_prci_corepllsel_use_corepll()
421 	u32 r;  in sifive_prci_hfpclkpllsel_use_hfclk()  local
423 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);  in sifive_prci_hfpclkpllsel_use_hfclk()
424 	r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;  in sifive_prci_hfpclkpllsel_use_hfclk()
425 	__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);  in sifive_prci_hfpclkpllsel_use_hfclk()
427 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);	/* barrier */  in sifive_prci_hfpclkpllsel_use_hfclk()
442 	u32 r;  in sifive_prci_hfpclkpllsel_use_hfpclkpll()  local
444 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
445 	r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
446 	__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
448 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);	/* barrier */  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
456 	u32 r;  in sifive_prci_pcie_aux_clock_is_enabled()  local
458 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);  in sifive_prci_pcie_aux_clock_is_enabled()
460 	if (r & PRCI_PCIE_AUX_EN_MASK)  in sifive_prci_pcie_aux_clock_is_enabled()
470 	u32 r __maybe_unused;  in sifive_prci_pcie_aux_clock_enable()
476 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);	/* barrier */  in sifive_prci_pcie_aux_clock_enable()
485 	u32 r __maybe_unused;  in sifive_prci_pcie_aux_clock_disable()
488 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);	/* barrier */  in sifive_prci_pcie_aux_clock_disable()
508 	int parent_count, i, r;  in __prci_register_clocks()  local
532 		r = devm_clk_hw_register(dev, &pic->hw);  in __prci_register_clocks()
533 		if (r) {  in __prci_register_clocks()
535 				 init.name, r);  in __prci_register_clocks()
536 			return r;  in __prci_register_clocks()
539 		r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev));  in __prci_register_clocks()
540 		if (r) {  in __prci_register_clocks()
542 				 init.name, r);  in __prci_register_clocks()
543 			return r;  in __prci_register_clocks()
551 	r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,  in __prci_register_clocks()
553 	if (r) {  in __prci_register_clocks()
554 		dev_err(dev, "could not add hw_provider: %d\n", r);  in __prci_register_clocks()
555 		return r;  in __prci_register_clocks()
573 	int r;  in sifive_prci_probe()  local
594 	r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);  in sifive_prci_probe()
595 	if (r) {  in sifive_prci_probe()
596 		dev_err(dev, "could not register reset controller: %d\n", r);  in sifive_prci_probe()
597 		return r;  in sifive_prci_probe()
599 	r = __prci_register_clocks(dev, pd, desc);  in sifive_prci_probe()
600 	if (r) {  in sifive_prci_probe()
601 		dev_err(dev, "could not register clocks: %d\n", r);  in sifive_prci_probe()
602 		return r;  in sifive_prci_probe()