Lines Matching refs:mult
52 unsigned int mult; in cpg_z_clk_recalc_rate() local
56 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
58 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, in cpg_z_clk_recalc_rate()
66 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
86 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate()
87 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
89 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
97 unsigned int mult; in cpg_z_clk_set_rate() local
100 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, in cpg_z_clk_set_rate()
102 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
107 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); in cpg_z_clk_set_rate()
190 unsigned int mult = 1; in rcar_gen4_cpg_clk_register() local
204 mult = cpg_pll_config->pll1_mult; in rcar_gen4_cpg_clk_register()
209 mult = cpg_pll_config->pll2_mult; in rcar_gen4_cpg_clk_register()
214 mult = cpg_pll_config->pll3_mult; in rcar_gen4_cpg_clk_register()
219 mult = cpg_pll_config->pll4_mult; in rcar_gen4_cpg_clk_register()
224 mult = cpg_pll_config->pll5_mult; in rcar_gen4_cpg_clk_register()
229 mult = cpg_pll_config->pll6_mult; in rcar_gen4_cpg_clk_register()
235 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen4_cpg_clk_register()
267 mult = 1; in rcar_gen4_cpg_clk_register()
297 __clk_get_name(parent), 0, mult, div); in rcar_gen4_cpg_clk_register()