Lines Matching refs:mult
57 unsigned int mult; in cpg_z_clk_recalc_rate() local
61 mult = 32 - val; in cpg_z_clk_recalc_rate()
63 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
70 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
77 mult = div64_ul(req->rate * 32ULL, prate); in cpg_z_clk_determine_rate()
78 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
80 req->rate = div_u64((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
88 unsigned int mult; in cpg_z_clk_set_rate() local
92 mult = div64_ul(rate * 32ULL, parent_rate); in cpg_z_clk_set_rate()
93 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
100 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; in cpg_z_clk_set_rate()
176 fixed->mult = 1; in cpg_rcan_clk_register()
283 unsigned int mult = 1; in rcar_gen2_cpg_clk_register() local
306 mult = cpg_pll_config->pll0_mult; in rcar_gen2_cpg_clk_register()
308 if (!mult) { in rcar_gen2_cpg_clk_register()
311 mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >> in rcar_gen2_cpg_clk_register()
317 mult = cpg_pll_config->pll1_mult / 2; in rcar_gen2_cpg_clk_register()
321 mult = cpg_pll_config->pll3_mult; in rcar_gen2_cpg_clk_register()
369 0, mult, div); in rcar_gen2_cpg_clk_register()