39 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_get_parent()  local
44 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_get_parent()
47 	ns = ns_to_src(&rcg->s, ns);  in clk_rcg_get_parent()
49 		if (ns == rcg->s.parent_map[i].cfg)  in clk_rcg_get_parent()
58 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)  in reg_to_bank()  argument
60 	bank &= BIT(rcg->mux_sel_bit);  in reg_to_bank()
66 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in clk_dyn_rcg_get_parent()  local
73 	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_get_parent()
76 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_get_parent()
77 	s = &rcg->s[bank];  in clk_dyn_rcg_get_parent()
79 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_get_parent()
96 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_set_parent()  local
99 	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_set_parent()
100 	ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);  in clk_rcg_set_parent()
101 	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);  in clk_rcg_set_parent()
198 static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)  in configure_bank()  argument
207 	bool banked_mn = !!rcg->mn[1].width;  in configure_bank()
208 	bool banked_p = !!rcg->p[1].pre_div_width;  in configure_bank()
209 	struct clk_hw *hw = &rcg->clkr.hw;  in configure_bank()
213 	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in configure_bank()
216 	bank = reg_to_bank(rcg, reg);  in configure_bank()
219 	ns_reg = rcg->ns_reg[new_bank];  in configure_bank()
220 	ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);  in configure_bank()
225 		mn = &rcg->mn[new_bank];  in configure_bank()
226 		md_reg = rcg->md_reg[new_bank];  in configure_bank()
229 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
233 		ret = regmap_read(rcg->clkr.regmap, md_reg, &md);  in configure_bank()
237 		ret = regmap_write(rcg->clkr.regmap, md_reg, md);  in configure_bank()
241 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
246 		if (rcg->ns_reg[0] != rcg->ns_reg[1]) {  in configure_bank()
248 			ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
253 			ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,  in configure_bank()
260 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
266 		p = &rcg->p[new_bank];  in configure_bank()
270 	s = &rcg->s[new_bank];  in configure_bank()
275 	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
280 		ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in configure_bank()
283 		reg ^= BIT(rcg->mux_sel_bit);  in configure_bank()
284 		ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);  in configure_bank()
293 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in clk_dyn_rcg_set_parent()  local
297 	bool banked_mn = !!rcg->mn[1].width;  in clk_dyn_rcg_set_parent()
298 	bool banked_p = !!rcg->p[1].pre_div_width;  in clk_dyn_rcg_set_parent()
300 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_set_parent()
301 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_set_parent()
303 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_set_parent()
306 		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);  in clk_dyn_rcg_set_parent()
307 		f.m = md_to_m(&rcg->mn[bank], md);  in clk_dyn_rcg_set_parent()
308 		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);  in clk_dyn_rcg_set_parent()
312 		f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;  in clk_dyn_rcg_set_parent()
314 	f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);  in clk_dyn_rcg_set_parent()
315 	return configure_bank(rcg, &f);  in clk_dyn_rcg_set_parent()
344 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_recalc_rate()  local
346 	struct mn *mn = &rcg->mn;  in clk_rcg_recalc_rate()
348 	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_recalc_rate()
349 	pre_div = ns_to_pre_div(&rcg->p, ns);  in clk_rcg_recalc_rate()
351 	if (rcg->mn.width) {  in clk_rcg_recalc_rate()
352 		regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);  in clk_rcg_recalc_rate()
356 		if (rcg->clkr.enable_reg != rcg->ns_reg)  in clk_rcg_recalc_rate()
357 			regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);  in clk_rcg_recalc_rate()
369 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in clk_dyn_rcg_recalc_rate()  local
373 	bool banked_p = !!rcg->p[1].pre_div_width;  in clk_dyn_rcg_recalc_rate()
374 	bool banked_mn = !!rcg->mn[1].width;  in clk_dyn_rcg_recalc_rate()
376 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_recalc_rate()
377 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_recalc_rate()
379 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_recalc_rate()
383 		mn = &rcg->mn[bank];  in clk_dyn_rcg_recalc_rate()
384 		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);  in clk_dyn_rcg_recalc_rate()
388 		if (rcg->ns_reg[0] != rcg->ns_reg[1])  in clk_dyn_rcg_recalc_rate()
394 		pre_div = ns_to_pre_div(&rcg->p[bank], ns);  in clk_dyn_rcg_recalc_rate()
438 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_determine_rate()  local
440 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req,  in clk_rcg_determine_rate()
441 					rcg->s.parent_map);  in clk_rcg_determine_rate()
447 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in clk_dyn_rcg_determine_rate()  local
452 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_determine_rate()
453 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_determine_rate()
454 	s = &rcg->s[bank];  in clk_dyn_rcg_determine_rate()
456 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map);  in clk_dyn_rcg_determine_rate()
462 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_bypass_determine_rate()  local
463 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_rcg_bypass_determine_rate()
465 	int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);  in clk_rcg_bypass_determine_rate()
474 static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)  in __clk_rcg_set_rate()  argument
477 	struct mn *mn = &rcg->mn;  in __clk_rcg_set_rate()
481 	if (rcg->mn.reset_in_cc)  in __clk_rcg_set_rate()
482 		reset_reg = rcg->clkr.enable_reg;  in __clk_rcg_set_rate()
484 		reset_reg = rcg->ns_reg;  in __clk_rcg_set_rate()
486 	if (rcg->mn.width) {  in __clk_rcg_set_rate()
488 		regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);  in __clk_rcg_set_rate()
490 		regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);  in __clk_rcg_set_rate()
492 		regmap_write(rcg->clkr.regmap, rcg->md_reg, md);  in __clk_rcg_set_rate()
494 		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in __clk_rcg_set_rate()
496 		if (rcg->clkr.enable_reg != rcg->ns_reg) {  in __clk_rcg_set_rate()
497 			regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);  in __clk_rcg_set_rate()
499 			regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);  in __clk_rcg_set_rate()
505 		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in __clk_rcg_set_rate()
508 	ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);  in __clk_rcg_set_rate()
509 	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);  in __clk_rcg_set_rate()
511 	regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);  in __clk_rcg_set_rate()
519 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_set_rate()  local
522 	f = qcom_find_freq(rcg->freq_tbl, rate);  in clk_rcg_set_rate()
526 	return __clk_rcg_set_rate(rcg, f);  in clk_rcg_set_rate()
532 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_set_floor_rate()  local
535 	f = qcom_find_freq_floor(rcg->freq_tbl, rate);  in clk_rcg_set_floor_rate()
539 	return __clk_rcg_set_rate(rcg, f);  in clk_rcg_set_floor_rate()
545 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_bypass_set_rate()  local
547 	return __clk_rcg_set_rate(rcg, rcg->freq_tbl);  in clk_rcg_bypass_set_rate()
565 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_bypass2_set_rate()  local
570 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_bypass2_set_rate()
574 	src = ns_to_src(&rcg->s, ns);  in clk_rcg_bypass2_set_rate()
575 	f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1;  in clk_rcg_bypass2_set_rate()
578 		if (src == rcg->s.parent_map[i].cfg) {  in clk_rcg_bypass2_set_rate()
579 			f.src = rcg->s.parent_map[i].src;  in clk_rcg_bypass2_set_rate()
580 			return __clk_rcg_set_rate(rcg, &f);  in clk_rcg_bypass2_set_rate()
633 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_pixel_set_rate()  local
641 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_pixel_set_rate()
645 	src = ns_to_src(&rcg->s, ns);  in clk_rcg_pixel_set_rate()
648 		if (src == rcg->s.parent_map[i].cfg) {  in clk_rcg_pixel_set_rate()
649 			f.src = rcg->s.parent_map[i].src;  in clk_rcg_pixel_set_rate()
668 		return __clk_rcg_set_rate(rcg, &f);  in clk_rcg_pixel_set_rate()
683 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_esc_determine_rate()  local
684 	int pre_div_max = BIT(rcg->p.pre_div_width);  in clk_rcg_esc_determine_rate()
707 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_esc_set_rate()  local
709 	int pre_div_max = BIT(rcg->p.pre_div_width);  in clk_rcg_esc_set_rate()
717 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_esc_set_rate()
721 	ns = ns_to_src(&rcg->s, ns);  in clk_rcg_esc_set_rate()
724 		if (ns == rcg->s.parent_map[i].cfg) {  in clk_rcg_esc_set_rate()
725 			f.src = rcg->s.parent_map[i].src;  in clk_rcg_esc_set_rate()
734 		return __clk_rcg_set_rate(rcg, &f);  in clk_rcg_esc_set_rate()
760 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_lcc_set_rate()  local
765 	f = qcom_find_freq(rcg->freq_tbl, rate);  in clk_rcg_lcc_set_rate()
770 	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);  in clk_rcg_lcc_set_rate()
771 	ret = __clk_rcg_set_rate(rcg, f);  in clk_rcg_lcc_set_rate()
774 		regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);  in clk_rcg_lcc_set_rate()
781 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_lcc_enable()  local
785 	return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);  in clk_rcg_lcc_enable()
790 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_lcc_disable()  local
794 	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);  in clk_rcg_lcc_disable()
799 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in __clk_dyn_rcg_set_rate()  local
802 	f = qcom_find_freq(rcg->freq_tbl, rate);  in __clk_dyn_rcg_set_rate()
806 	return configure_bank(rcg, f);  in __clk_dyn_rcg_set_rate()